initial:
reference library(mw), link library(db),
create_mw_lib, read_verilog, link
create_floorplan
tap cell, spare cell,
power network
place:
set place scenarios
set routing layers （for RC calculation）
set crpr, recovery, gating_check
remove_ideal_network -all
set_ideal_network [all_fanout -flat -clock_tree] ( func + scan )
place_opt
cts：
set cts scenario
set cts reference buf / inv
set cts exceptions (float pin, stop pin)
remove_ideal_network, set_propagated_clock
clock_opt -only_cts -no_clock_route
post-cts opt:
remove_ideal_network, set_propagated_clock
disable ck cells
set_fix_hold [all_clocks]
clock_opt -psyn
clock route:
set nondefault routing rule for clock route
route:
set_xtalk_route_options
route_zrt_auto -max 20
insert filler cell
route_zrt_detail incremental -max 5
insert_metal_filler