module qin
(
input clk,
output reg beep,
input [3:0] col,
output [3:0] row_data,
output [7:0]out ,
input rst_n
);
wire [3:0] key;
wire en;
parameter STOP=0,
DOD=47708,//262,
RED=42516,//294,
MD=37876,//330,
FAD=35816,//349,
SOD=31886,//392,
LAD=28408,//440,
SID=25302,//494,
DOM=23900,//523,
REM=21294,//587,
MM=18968,//659,
FAM=17908,//698
SOM=15943,//784
LAM=14204,//880
SIM=12651,//988
DOG=11950,//1046
REG=10638;//1175
reg f[15:0];
reg[19:0] cnt1;
reg[19:0] cnt2;
reg[19:0] cnt3;
reg[19:0] cnt4;
reg[19:0] cnt5;
reg[19:0] cnt6;
reg[19:0] cnt7;
reg[19:0] cnt8;
reg[19:0] cnt9;
reg[19:0] cnt10;
reg[19:0] cnt11;
reg[19:0] cnt12;
reg[19:0] cnt13;
reg[19:0] cnt14;
reg[19:0] cnt15;
reg[19:0] cnt16;
juzhen1 juzhen_ut
(
.clk(clk),
.rst_n(rst_n),
.col_data(col),
.row_data(row_data),
.key_flag(),
.key_flag_r0(en),
.key_value(key),
.out(out)
);
always@(posedge clk)
begin
if(cnt1==DOD*2-1)begin f[0]<=1;cnt1<=0;end
else if(cnt1<=DOD)begin f[0]<=1;cnt1<=cnt1+1;end
else begin cnt1<=cnt1+1;f[0]<=0;end
//always@(posedge clk)
if(cnt2==RED*2-1)begin f[1]<=1;cnt2<=0;end
else if(cnt2<=RED)begin f[1]<=1;cnt2<=cnt2+1;end
else begin cnt2<=cnt2+1;f[1]<=0;end
//always@(posedge clk)
if(cnt3==MD*2-1)begin f[2]<=1;cnt3<=0;end
else if(cnt3<=MD)begin f[2]<=1;cnt3<=cnt3+1;end
else begin cnt3<=cnt3+1;f[2]<=0;end
//always@(posedge clk)
if(cnt4==FAD*2-1)begin f[3]<=1;cnt4<=0;end
else if(cnt4<=FAD)begin f[3]<=1;cnt4<=cnt4+1;end
else begin cnt4<=cnt4+1;f[3]<=0;end
//always@(posedge clk)
if(cnt5==SOD*2-1)begin f[4]<=1;cnt5<=0;end
else if(cnt5<=SOD)begin f[4]<=1;cnt5<=cnt5+1;end
else begin cnt5<=cnt5+1;f[4]<=0;end
//always@(posedge clk)
if(cnt6==LAD*2-1)begin f[5]<=1;cnt6<=0;end
else if(cnt6<=LAD)begin f[5]<=1;cnt6<=cnt6+1;end
else begin cnt6<=cnt6+1;f[5]<=0;end
//always@(posedge clk)
if(cnt7==SID*2-1)begin f[6]<=1;cnt7<=0;end
else if(cnt7<=DOD)begin f[6]<=1;cnt7<=cnt7+1;end
else begin cnt7<=cnt7+1;f[6]<=0;end
//always@(posedge clk)
if(cnt8==DOM*2-1)begin f[7]<=1;cnt8<=0;end
else if(cnt8<=DOM)begin f[7]<=1;cnt8<=cnt8+1;end
else begin cnt8<=cnt8+1;f[7]<=0;end
//always@(posedge clk)
if(cnt9==REM*2-1)begin f[8]<=1;cnt9<=0;end
else if(cnt9<=REM)begin f[8]<=1;cnt9<=cnt9+1;end
else begin cnt9<=cnt9+1;f[8]<=0;end
//always@(posedge clk)
if(cnt10==MM*2-1)begin f[9]<=1;cnt10<=0;end
else if(cnt10<=MM)begin f[9]<=1;cnt10<=cnt10+1;end
else begin cnt10<=cnt10+1;f[9]<=0;end
//always@(posedge clk)
if(cnt11==FAM*2-1)begin f[10]<=1;cnt11<=0;end
else if(cnt11<=FAM)begin f[10]<=1;cnt11<=cnt11+1;end
else begin cnt11<=cnt11+1;f[10]<=0;end
//always@(posedge clk)
if(cnt12==SOM*2-1)begin f[11]<=1;cnt12<=0;end
else if(cnt12<=SOM)begin f[11]<=1;cnt12<=cnt12+1;end
else begin cnt12<=cnt12+1;f[11]<=0;end
//always@(posedge clk)
if(cnt13==LAM*2-1)begin f[12]<=1;cnt13<=0;end
else if(cnt13<=LAM)begin f[12]<=1;cnt13<=cnt13+1;end
else begin cnt13<=cnt13+1;f[12]<=0;end
//always@(posedge clk)
if(cnt14==SIM*2-1)begin f[13]<=1;cnt14<=0;end
else if(cnt14<=SIM)begin f[13]<=1;cnt14<=cnt14+1;end
else begin cnt14<=cnt14+1;f[13]<=0;end
//always@(posedge clk)
if(cnt15==DOG*2-1)begin f[14]<=1;cnt15<=0;end
else if(cnt15<=DOG)begin f[14]<=1;cnt15<=cnt15+1;end
else begin cnt15<=cnt15+1;f[14]<=0;end
//always@(posedge clk)
if(cnt16==REG*2-1)begin f[15]<=1;cnt16<=0;end
else if(cnt16<=REG)begin f[15]<=1;cnt16<=cnt16+1;end
else begin cnt16<=cnt16+1;f[15]<=0;end
end
always@(key[3:0] or rst_n )
begin
if(!rst_n) beep=0;
if(en) begin
case(key[3:0])
4'd0: begin beep<=f[0]; end
4'd1:begin beep<=f[1]; end
4'd2:begin beep<=f[2]; end
4'd3:begin beep<=f[3]; end
4'd4:begin beep<=f[4];end
4'd5:begin beep<=f[5];end
4'd6:begin beep<=f[6]; end
4'd7:begin beep<=f[7];end
4'd8:begin beep<=f[8];end
4'd9:begin beep<=f[9];end
4'd10:begin beep<=f[10];end
4'd11:begin beep<=f[11];end
4'd12:begin beep<=f[12];end
4'd13:begin beep<=f[13];end
4'd14:begin beep<=f[14]; end
4'd15:begin beep<=f[15];end
default:beep<=0;
endcase
end
else beep=0;
end
endmodule
基于4*4的矩阵键盘 赋予每个按键一个音符，通过蜂鸣器（无源）输出