简单ALU（算术逻辑单元）的verilog实现

2013-06-14 21:39:56

简单ALU（算术逻辑单元）的verilog实现，可实现两数相加、相减，或一个数的加1、减1操作。

小结：

• 要学会看RTL图，能够根据RTL图大致判断功能的正确性

代码：

module alu_add_sub(
                        rst_n,
                        clk,
                        oper_cmd,
                        oper_data,
                        dout
                             );
                             
parameter DATA_SIZE = 4'd8;    //操作数宽度                         

input rst_n;
input clk;

input [1:0] oper_cmd;
input [2*DATA_SIZE - 1:0] oper_data;

output [DATA_SIZE:0] dout;

reg [1:0] oper_cmd_r;
reg [2*DATA_SIZE - 1:0] oper_data_r;

wire  [2*DATA_SIZE:0] add_sub_oper;

reg [DATA_SIZE:0] dout_tmp;
reg [DATA_SIZE:0] dout;

//输入数据打一拍
always@(posedge clk)
    if(!rst_n)
        begin
            oper_cmd_r <= 8'd0;
            oper_data_r <= 16'd0;
        end
    else
        begin
            oper_cmd_r <= oper_cmd;
            oper_data_r <= oper_data;
        end    

//根据输入数据，求操作码，相当于指令译码
assign add_sub_oper = add_sub_func(oper_cmd_r,oper_data_r);

//根据译码结果，求输出
always@(posedge clk)
if(!rst_n)
    begin
        dout_tmp <= 9'd0;
    end
else
    begin
        if(add_sub_oper[2*DATA_SIZE])
            dout_tmp <= add_sub_oper[2*DATA_SIZE-1 : DATA_SIZE] + add_sub_oper[DATA_SIZE-1 : 0];
        else
            dout_tmp <= add_sub_oper[2*DATA_SIZE-1 : DATA_SIZE] - add_sub_oper[DATA_SIZE-1 : 0];
    end

//输出数据打一拍
always@(posedge clk)
    if(!rst_n)
            dout <= 9'd0;
    else
        dout <= dout_tmp;

//指令译码函数
function [2*DATA_SIZE:0] add_sub_func;  //关键字function标志函数开始
    input [1:0] oper_cmd;
    input [2*DATA_SIZE - 1:0] oper_data;

    reg [1:0] mode;
    reg [DATA_SIZE - 1:0] oper1;
    reg [DATA_SIZE - 1:0] oper2;

    //always@(oper_cmd or oper_data)
    begin     //函数体须在过程块中
        case(oper_cmd)
            2'b00 :         //两数相加
                begin
                    mode = 1;
                    oper1 = oper_data[2*DATA_SIZE - 1:DATA_SIZE];
                    oper2 = oper_data[DATA_SIZE - 1:0];
                end
            2'b01 :     //加1
                begin
                    mode = 1;
                    oper1 = oper_data[2*DATA_SIZE - 1:DATA_SIZE];
                    oper2 = 1'b1;
                end
            2'b10 :         //两数相减
                begin
                    mode = 0;
                    oper1 = oper_data[2*DATA_SIZE - 1:DATA_SIZE];
                    oper2 = oper_data[DATA_SIZE - 1:0];
                end
            default :     //减1
                begin
                    mode = 0;
                    oper1 = oper_data[2*DATA_SIZE - 1:DATA_SIZE];
                    oper2 = 1'b1;
                end    
        endcase    
        add_sub_func = {mode,oper1,oper2};
    end

endfunction  //关键字endfunction标志函数结束

endmodule

testbench：

module alu_add_sub_tb;

    // Inputs
    reg rst_n;
    reg clk;
    reg [1:0] oper_cmd;
    reg [15:0] oper_data;

    // Outputs
    wire [8:0] dout;

    // Instantiate the Unit Under Test (UUT)
    alu_add_sub uut (
        .rst_n(rst_n), 
        .clk(clk), 
        .oper_cmd(oper_cmd), 
        .oper_data(oper_data), 
        .dout(dout)
    );
    
    parameter CLK_PERIOD = 10;

    initial begin
        rst_n = 0;
        clk = 1;
        oper_cmd = 0;
        //oper_data = 0;

        #100;
        rst_n = 1;
        
        # (10*CLK_PERIOD) oper_cmd = 2'b00;  //两数相加测试
        
        # (10*CLK_PERIOD) oper_cmd = 2'b01;     //加1测试
        
        # (10*CLK_PERIOD) oper_cmd = 2'b10;     //两数相减测试
        
            # (10*CLK_PERIOD) oper_cmd = 2'b11;    //减1测试
 
    end
    
    always #(CLK_PERIOD/2) clk = ~clk;
    
    always@(posedge clk)
    if(!rst_n)
        begin
            oper_data[15:8] = 0;
            oper_data[7:0] = 0;
        end
    else
        begin
            oper_data[15:8] = oper_data[15:8] + 1;
            oper_data[7:0] = oper_data[7:0] + 1;
        end
      
endmodule

分析仿真结果，代码满足所需功能。

综合RTL图：

（xilinx的RTL图很底层，不太容易看懂）