Ans: Clocking block can be declared using the keywords clocking and endclocking. A clocking block is mainly used in the testbench in order to avoid race conditions. Clocking blocks are used to assemble all the signals. They are useful in separating clocking activities from its main data activities. The declaration and instantiation of clocking block can both occur inside the module.
Ans: Modports define directions of ports as if they are declared inside the module. To restrict interface access within module modports are used. Modports can have inputs, outputs and inout ports also.
Ans: Interfaces enables the connectivity between the modules. It allows the smooth flow of design between the modules. The design can also be reused using interfaces. Using interfaces, we can replace a group of names with a single name which is helpful in reducing the size of program.
Ans: A virtual interface can be used a reference to existing interface. It allows the subprogram to operate in parts of design.
Ans: Class is composed of set of members that describe how an instance of class or object is constructed and how it behaves.
Eg: class class name{
member1;
---------------}
object name;
Ans: Program block is mainly used in the writing of testbench. It is defined with a set of keywords, program and endprogram. It separates the testbench from the device under test. This block works well in the hardware description of the modules. Program block is also used to avoid race conditions.
Ans: Mailbox is communication mechanism that allows the exchange of the messages between the processes. Mailboxes are helpful in the transmission and receiving of the data in a systematic way.
Ans: A semaphore is like a bucket and used in synchronization. They are inbuilt in systemveriolg. When a semaphore is allocated, the keys are allocated to each and every bucket. The number is fixed. The keys are not identical. Processes using semaphores must definitely have a key from bucket before they start the execution process.
Ans: Code specified in program blocks and pass/fail code from property expressions are scheduled in reactive scheduler.
Ans: The variables in the class can be declared random using the keywords: rand and randc. Dynamic and associative arrays can be declared using rand or randc keywords.
Ans: Variables declared with rand keywords are standard random variables. Their values are uniformly distributed over their range. Values declared with randc keyword are randomly distributed. They are cyclic in nature. They support only bit or enumerated data types. The size is limited.
Ans: The always_ff can be used to model sequential logic behavior. The always_ff is always synthesizable.
Ans: For overriding the values in the class, static function is used. Whereas in automatic, when one task is called, two separate memories will be allocated.
Ans: Assigning arrays in systemverilog uses the replicate operators. Eg: int n[1:2][1:3]={{0,1,2),{3{4}}};
Ans: There are two terminologies
associated with the arrays in systemverilog. Packed and unpacked
arrays. When the dimensions of arrays are
declared
before the object name is referred to as “packed arrays”. The
“unpacked array” term is used to refer when the dimensions are
declared
after the object name. The memory allocation of both packed and
unpacked arrays also differs.
E.g.: int [7:0] c1; //packed array
reg r[7:0] //unpacked array
Ans: An assertion specifies a behavior of the system. They a re primarily used to validate a behavior of design. Assertions can also be used to provide functional coverage and generate input stimulus for validation.
Ans: Is called as cycle delay syntax: ## 2; fifo.wdata < =8’hAA; //wait for 2 default clocking cycles, then drive wdata.
Ans: When we use the same function name in both the base and derived classes, the function in the base class is declared as virtual. The class is preceded using the keyword virtual before its normal declaration.
Ans: Assertions are mainly used to check the behavior of the design whether it is working correctly or not. They are useful in providing the functional coverage information .i.e. how good the test is and whether the design meets all the requirements for testing. There are mainly two types of assertions in systemverilog. They are: immediate assertions and concurrent assertions.
Ans: Wire is basic data type which does
not drive strength
a) wire is used for designing combinational
logic. We can assign a single value to a wire by using the assign
statement. Wire cannot store any data.
b) reg data type can be used for storage purpose. reg is used for
designing both sequential and combinational circuits. reg data
types can be driven from initial and always block .
c) logic data types are similar to reg data types
.
Ans: A callback is a built in systemverilog task/function. Suppose if we are transmitting a data using mailbox and you are sending data from design to transmitter. If you want to get back the data and you need the same data to put back in the scoreboard for comparison, this is called callback. Any change in the transmitted data can be achieved using the callback routine. Generally callbacks are called bfore transmission and after receiving the data.
Ans: Using program block and clocking block.
Ans: Active region: simulation of design
codes in modules.
Observed region: checking the system verilog
assertions.
Reactive region: executing the testbench code.
Postponed region: sampling the design signals for test bench
inputs.
Ans: Functional coverage and code coverage.
Ans: It can be detected using a property checking with assertion.
Ans: A Mutex object only allows one thread into a controlled section. They cannot be executed by more than one thread in a concurrent manner. A mutex can be released only through thread.
Ans: If we want to produce the same simulation results, seed is used. But the seed number should be same to perform the operation.
Ans: Functional coverage: Functional coverage determines how much functionality of the design has been exercised. Functional assertions are used to check whether each and every corner of the design is explored and functions properly. Code coverage: This will give information about how many lines are executed, how many times each expression is executed. It describes the level up to which the code has been tested.
Ans: code: High functional: High - You are
most likely done
code: High functional: Low - Still need to
run more simulation or improve test bench
code: Low functional: High - Probably missing functional coverage
points
code: Low functional: Low - Still need to run more simulation or
improve test bench
Ans: We can mention it as #5ns.
Ans: By specifying constraints, users can easily create tests that are very difficult to reach corners of the design. Sytemverilog allows users to specify constraints in compact and declarative way. Random values are generated to meet the constraints.
Ans: Random constraints, user defined constraints, inline constraints, if-else constraints and global constraints.
Ans: If the given expression is true, all the constraints in the first constraint block should be satisfied, otherwise all of the constraints in the else constraint block will be satisfied.
Ans: A derived class by default has the
properties and methods of the base class or parent class. This is
called inheritance.
Syntax: class Derived extends
BaseClass;
// method declarations.
endclass
Ans: The module is the basic building block in verilog which is used in creating a design. Systemverilog adds a new block called program block which can be declared using the keywords program and endprogram. The program block separates the design and testbench. The program block and module differs in syntax also.
Ans: Systemverilog adds a final block that executes the end of simulation. There is nothing to be executed after the final block. It is the end of simulation. Final block should not have any delays.
Ans: When array is declared, memory is allocated for the elements of array when the program starts. Memory is allocated to the array only when the arrays are declared in the program. The memory remains allocated during the lifetime of the program. This is called static array. It may sometimes happen that we don’t know how large an array we will need. In this case, it is convenient to allocate an array while the program is running. This is called dynamic array. Dynamic array is a one dimensional array.
Ans: Abstract classes are those which can be used for creation of handles. Their methods and constructors and can be used by the class or extended class. They are used to generalize the super class from which child classes can share its methods.
Ans: $random and $random are both system
functions.
1. $random returns a 32-bit signed random
number whenever it is added.
2. $urandom returns a 32-bit unsigned random number whenever it is
added. It a newly added system function in
systemverilog.
Ans: Systemverilog provides $cast system
task to assign values to variables that may not be valid because of
differing data type. $cast can be called as
either a task or a function. $cast is basically used in dynamic
casting. For more accurate checking of values, $cast is used.
Syntax: $cast(des_val, eval_expr)
Ans: Mailbox is similar to a queue, which allows only atomic operations. They can be bounded/unbounded. Get/put task is used to suspend a bounded mailbox. That’s why mailbox is used more for communication between threads. Queues are large structures. Inserting data in queues is very difficult.
Ans: Constraints in systemverilog are bidirectional by default. That means they do not follow any sequence in which the constraints are mentioned. All the variables are looked simultaneously.
Ans: Over specifying the solving order might result in circular dependency. There is no solution for circular dependency. The constraint solver might give error/warning or no constraining.
Ans: The super keyword is used from the derived class to refer to the members of the derived class. If we want to access members of derived class that are overridden by the derived class, super keyword is used. Super keyword cannot be accessed directly.
Ans: This keyword is used to call the parameters of same class.
Ans: Skews are numbers that are indicated before the input and output ports. A skew number indicated before an input defines that the input is sampled before the clocking event occurs, ie a posedge or negedge occurs. A skew number in the output indicates that the output is synchronized and then sent to the clocking blocks. A skew must be a constant expression. It can also be specified as a parameter.
Ans: Dynamic data types and dynamic memory allocations in systemverilog makes us easy to write scoreboards. Scoreboard is used to store the expected output of the device under test. It implements the same functionality as DUT. It uses higher level of constructs.
Ans: The main purpose of dividing the time slots in systemverilog is to provide interaction between the design and the testbench.
Ans: In systemverilog we can create a static variable inside the class. But this variable has a limited scope. The variable declared static is shared among the other variables in the class. A static variable is usually instantiated inside the declaration.
Ans: 1) Packet count match
2) Error
3) Error count
4) Interface idle count
5) Global Time out
Ans: Objects in systemverilog can be declared as public and private. Public declarations are accessible from outside that object, i.e. they are accessible by the users. By default declarations in systemverilog are public.
Ans: In order to make the declarations private, local attribute is used. Once the data is declared as local, it can be accessed on in the particular class.