添加altera 库
实例：
把建立lpm_mux IP时生成的.v文件lpm_mux_ip.v和编写的测试脚本文件放在一起，在modelsim中建立工程，把下面两个文件添加到工程中
直接compile ->simulation会报错
但在simulation library中添加上自己编译添加的lpm库后，就可以了
附录：
简单的测试脚本：
module lpm_mux_ip_tb;
reg [7:0] dataa ;
reg [7:0] datab ;
reg clock;
wire[15:0] result;
lpm_mux_ip u_lpm_mux_ip(
.dataa(dataa),
.datab(datab),
.clock(clock),
.result(result)
);
initial
begin
#0 dataa = 0;
datab = 0;
clock = 0;
end
always
begin
#10 clock = ~clock;
end
always
begin
#20 dataa = dataa + 1;
datab = datab + 1;
end
endmodule
IP核生成的文件：
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mux_ip (
clock,
dataa,
datab,
result);
input clock;
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule