Audio Clocking
音频时钟
==============
This text describes the audio clocking terms in ASoC and digital audio in
general. Note: Audio clocking can be complex!
本文本总体描述ASoC和数字音频中的音频时钟条款。
Note：Audio Clock 是一个很复杂的东东
Master Clock
主时钟
------------
Every audio subsystem is driven by a master clock (sometimes referred to as MCLK or SYSCLK). This audio master clock can be derived from a number of sources (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.
每个数字音频子系统都是由主时钟来驱动的（有时称为MCLK或SYSCLK）。音频主时钟可以派生于多种源（如晶振，锁相环，处理器时钟）。负责产生正确的音频播放和捕获采样率。
Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at a set frequency (i.e. crystals).
有些主时钟是可配置的（如基于锁相环或处理器的时钟），它们可以通过软件改变速度（依赖于系统应用和省电的考虑）。另一些主时钟则是固定于一个特定的频率值（如晶振）。
Master Clock
主时钟
------------
Every audio subsystem is driven by a master clock (sometimes referred to as MCLK or SYSCLK). This audio master clock can be derived from a number of sources (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.
每个数字音频子系统都是由主时钟来驱动的（有时称为MCLK或SYSCLK）。音频主时钟可以派生于多种源（如晶振，锁相环，处理器时钟）。负责产生正确的音频播放和捕获采样率。
Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at a set frequency (i.e. crystals).
有些主时钟是可配置的（如基于锁相环或处理器的时钟），它们可以通过软件改变速度（依赖于系统应用和省电的考虑）。另一些主时钟则是固定于一个特定的频率值（如晶振）。
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数字音频时钟
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as BCLK). This clock is used to drive the digital audio data across the link
between the codec and CPU.
数字音频接口往往是由一个位时钟来驱动的（通常记为BCLK）。这个时钟用于驱动数字音频数据在解码器与处理器间的传输。
The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
runs at exactly the sample rate (LRC = Rate).
数字音频接口还有一个帧时钟，用来指示一帧音频的开始。该时钟有时记为LRC（left right clock）或FRAME。该时钟严格工作于采样率上。
Bit Clock can be generated as follows:-
位时钟可以有如下产生方式：
BCLK = MCLK / x
or
BCLK = LRC * x
or
BCLK = LRC * Channels * Word Size
This relationship depends on the codec or SoC CPU in particular. In general
it is best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and word size) to save on power.
这个关系依赖于解码器，特别是板上处理器。大体上讲，最好将位时钟尽可能低速（取决于你的采样率，通道数和字长）以省电。
It is also desirable to use the codec (if possible) to drive (or master) the
audio clocks as it usually gives more accurate sample rates than the CPU.
可能的话，最好使用解码器来驱动（或控制）音频时钟，因为通常它给出的采样率比处理器更精确。
This relationship depends on the codec or SoC CPU in particular. In general
it is best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and word size) to save on power.
这个关系依赖于解码器，特别是板上处理器。大体上讲，最好将位时钟尽可能低速（取决于你的采样率，通道数和字长）以省电。
It is also desirable to use the codec (if possible) to drive (or master) the
audio clocks as it usually gives more accurate sample rates than the CPU.
可能的话，最好使用解码器来驱动（或控制）音频时钟，因为通常它给出的采样率比处理器更精确。