1 OMAPL138-AINTC定义：AINTC是SOC片上系统中断和ARM9内核中断之间的接口，ARM9内核中断分为IRQ和FIQ两种；
1.1 101个系统中断
1.2 32个中断通道
1.3 通道0和1映射FIQ快速中断，通道2-31映射IRQ中断
1.4 每个系统中断可单独使能和禁止
1.5 ARM9内核中断可使能和禁止
1.6 硬中断优先级管理
2 OMAPL138-AINTC之中断映射
2.1 101个片上系统中断可映射任意32个中断通道
2.2 多个系统中断可映射到一个中断通道
2.3 一个系统中断不能映射到多个中断通道
2.4 中断通道0-1映射到ARM内核的快速中断FIQ
2.5 中断通道2-31映射到ARM内核的普通中断IRQ
2.6 中断通道号越小，中断优先级越高，同一个中断通道中中断号越小，中断优先级越高
2.7 AINTC中断分配表 0-100--101个中断号，其中3-10,26,62是系统预留，没有使用
3 OMAPL138-AINTC之中断调度策略
3.1 AINTC是系统中断映射到内核中断的接口，其中系统中断是由片上设备产生，AINTC接收系统中断，并将之映射到中断通道。中断通道负责中断优先级管
理，系统中断的电平既可以是电平触发，也可以是脉冲触发；
3.2 AINTC功能模块包括中断处理processing，中断使能enabling，中断状态检测status，中断通道映射channel mapping，中断优先级调度prioritization， 中断向量化管理vectorization，中断调试debug，内核接口host interfacing；
3.3 中断处理processing单元将慢速和异步中断统一转化为高电平脉冲触发方式；
3.4 中断使能enabling单元可单独对中断进行使能或禁止，步骤分为三步，第一步Enable global host interrupts，All host interrupts are enabled by setting the ENABLE bit in the global enable register (GER). Individual host interrupts are enabled or disabled from their individual enables
and are not overridden by the global enable；第二步Enable host interrupt lines. Host interrupt lines (FIQ and IRQ) can be enabled through one of two methods: a Set the desired mapped bit(s) in the host interrupt enable register (HIER)， b Write the host interrupt index (0-1) to the host interrupt enable indexed set register (HIEISR) for every interrupt line to enable；第三步Enable system interrupts. System interrupts can be individually enabled through one of two methods:a. Set the desired mapped bit(s) in the system interrupt enable set registers (ESR1-ESR3), or
b. Write the system interrupt index (0-90) to the system interrupt enable indexed set register (EISR) for every system interrupt to enable；
3.5 中断状态检测Interrupt Status Checking单元，反映了当前中断状态寄存器清除后，是否有中断的发生，有两类中断挂起状态，raw+enable，其中raw对应的中断源是没有使能条件下的中断状态，enable反映的是在有中断是使能条件下的中断挂起状态，The enabled status of system interrupts is captured in system interrupt status enabled/clear registers (SECR1-SECR3)；
3.6 中断通道映射，通道映射寄存器CMRn确定32个中断通道和系统中断源的对应关系，4个中断源对应一个通道映射寄存器CMR；
3.7 内核中断映射，ARM9内核有两个中断输入：FIQ+IRQ，中断通道0-1对应FIQ，中断通道2-31对应IRQ；
3.8 中断优先级管理策略Interrupt Prioritization单元，在多个中断源对应一个中断通道，多个中断通道对应一个内核中断的情况下，确定唯一一个中断服务交与CPU执行时必要的，有两级中断优先级管理，第一级优先级管理策略是从32个个中断通道中选择一个进入内核中断，中断通道序列越小，优先级越高。第二级优先级管理策略是在第一级优先级管理选择了中断通道的基础上，由进入中断通道的中断源的向量号确立中断服务，中断向量号越小，优先级越高。优先级管理是由AINTC来实现的；
3.9 中断嵌套Interrupt Nesting，Nesting is available in 1 of 3 methods selectable by the NESTMODE bit in the control register (CR):
第二种中断嵌套方法：Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting level is set to its channel priority for just that host interrupt, and other host interrupts do not have their nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers (HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt.
The recommended approach is the automatic host interrupt nesting method (second method). Because higher priority interrupts can preempt lower priority interrupts in this method, a software stack is used to keep track of nest priorities. The base stack value should be initialized to the default nest priority of the application. Take the following steps within the ARM hardware interrupt service routine to handle interrupts
using host interrupt priority nesting:
1. Disable the ARM hardware interrupt.
2. Clear the OVERRIDE bit in the host interrupt nesting level register n (HINLRn) to expose the priority level of the active interrupt.
3. Push the active (or desired) interrupt priority value into the nest priority stack.
4. Write the active (or desired) priority level into HINLRn by setting the OVERRIDE bit.
5. Calculate and store the ISR address for the active interrupt. Unfreeze the host interrupt prioritized index register n (HIPIRn) and the host interrupt prioritized vector register n (HIPVRn), if the PRHOLDMODE bit in the control register (CR) is set.
6. Clear the system interrupt status by setting the appropriate bit in the system interrupt status enabled/clear register n (SECRn) or by writing the appropriate index to the system interrupt status indexed clear register (SICR).
7. Acknowledge and enable the ARM hardware interrupt.
8. Execute the ISR at the address stored from step 5. During this step, interrupts enabled by the new nest priority level will be able to preempt the ISR.
9. Disable the ARM hardware interrupt.
10. Discard the most recent priority level in the nest priority stack and restore the previous priority level to HINLRn by setting the OVERRIDE bit.
11. Enable the ARM hardware interrupt.
3.10 中断向量Interrupt Vectorization单元：Vectorization uses a base and universal size where all the ISR code is placed in a contiguous memory region with each ISR code a standard size. For this calculation, the vector base register (VBR) is programmed by software to hold the base address of all the ISR code and the vector size register (VSR) is programmed for the size in words between ISR code for each system interrupt. The index number of each system interrupt is used to calculate the final offset. The specific system interrupt ISR address is then calculated as:
ISR address = base + (index ´ size)
There is also a special case when there is no interrupt pending and then the ISR address is the ISR Null address. This is in case the vector address is executed when there is no pending interrupt so that a Null handler can be in place to just return from the interrupt. The vector null address register (VNR) holds the address of the ISR null address. When there is a pending interrupt then the ISR address is calculated as
exact base + offset for that interrupt number.
3.11 中断状态清除Interrupt Status Clearing For clearing the status of an interrupt, whose interrupt number is N, write a 1 to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR3). System interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear register (SICR)；
3.12 中断禁止Interrupt Disabling，For disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable clear registers (ECR1-ECR3). System interrupt N can also be disabled by writing the value N in the system interrupt enable indexed clear register (EICR) ；