认识zedboard板子也有半个多月了，期间有不少杂事，学的也不是很认真，最近几天在学习如何利用AXI总线进行PS和PL部分的相互通信，利用自定义的IP核实现了简易的计算功能（只有加减），下面对实验的过程和自己的理解进行一下记录。
首先本次试验的目的是做一个建议的计算器，通过zedboard上的sw1，sw2标识操作(01表示加法操作，10表示剪发操作)，另外通过led灯进行结果的显示，通过串口进行操作数的输入，而后利用FPGA进行运算，串口输出结果。
实验步骤：
- 首先在xps中进行工程的建立，导入配置文件(.xml);
- 而后进行自定义IP核的生成，这部分在下面进行详细记录；
- 将由xps完成的工程导出，进行ps端应用程序的编写
XPS工程的建立，这部分较为简单，只用简单图示进行记录
- 首先建立工程，在这里听师兄讲的，我理解为建立工程时用Base System Builder的好处是不需要对基础的一些信息进行配置，这样就能省去很多开发的麻烦，更深层次的就不能体会了。。。
- 建立工程后选择Avnet，在Base System Builder界面将右侧不用的外设进行remove掉，而后完成对工程的建立
- 利用Hardware下的Create or import Peripheral建立自定义的IP核(在此我理解为这一步仅为对IP核的一些基础信息的配置，至于IP核具体实现的功能和引出的端口还需要对用户逻辑等信息进行配置)，在选择寄存器的个数时，由于本工程中涉及到SW，LED和进行计算时对操作数和结果的存储，因此共需要五个寄存器
在完成此IP的基本配置信息之后，进行用户逻辑和端口号的配置
4. 首先找到工程目录下的pcoresmy_calc_v1_v1_00_ahdlverilog的user_logic.v文件对用户逻辑进行修改，本工程中设计到的用户逻辑很简单，根据sw前两位的值判断运算方式，而后利用运算数进行运算结果在led灯上进行显示，代码如下，对加入的代码部分进行解释，并加入我的理解
代码：
1 //---------------------------------------------------------------------------- 2 // user_logic.v - module 3 //---------------------------------------------------------------------------- 4 // 5 // *************************************************************************** 6 // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** 7 // ** ** 8 // ** Xilinx, Inc. ** 9 // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** 10 // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** 11 // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** 12 // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** 13 // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** 14 // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** 15 // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** 16 // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** 17 // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** 18 // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** 19 // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** 20 // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** 21 // ** FOR A PARTICULAR PURPOSE. ** 22 // ** ** 23 // *************************************************************************** 24 // 25 //---------------------------------------------------------------------------- 26 // Filename: user_logic.v 27 // Version: 1.00.a 28 // Description: User logic module. 29 // Date: Fri Jul 19 15:24:36 2013 (by Create and Import Peripheral Wizard) 30 // Verilog Standard: Verilog-2001 31 //---------------------------------------------------------------------------- 32 // Naming Conventions: 33 // active low signals: "*_n" 34 // clock signals: "clk", "clk_div#", "clk_#x" 35 // reset signals: "rst", "rst_n" 36 // generics: "C_*" 37 // user defined types: "*_TYPE" 38 // state machine next state: "*_ns" 39 // state machine current state: "*_cs" 40 // combinatorial signals: "*_com" 41 // pipelined or register delay signals: "*_d#" 42 // counter signals: "*cnt*" 43 // clock enable signals: "*_ce" 44 // internal version of output port: "*_i" 45 // device pins: "*_pin" 46 // ports: "- Names begin with Uppercase" 47 // processes: "*_PROCESS" 48 // component instantiations: "<ENTITY_>I_<#|FUNC>" 49 //---------------------------------------------------------------------------- 50 51 `uselib lib=unisims_ver 52 `uselib lib=proc_common_v3_00_a 53 54 module user_logic 55 ( 56 // -- ADD USER PORTS BELOW THIS LINE --------------- 57 // --USER ports added here 58 SW_In, //The operator 59 LED_Out, //Show some information 60 // -- ADD USER PORTS ABOVE THIS LINE --------------- 61 62 // -- DO NOT EDIT BELOW THIS LINE ------------------ 63 // -- Bus protocol ports, do not add to or delete 64 Bus2IP_Clk, // Bus to IP clock 65 Bus2IP_Resetn, // Bus to IP reset 66 Bus2IP_Data, // Bus to IP data bus 67 Bus2IP_BE, // Bus to IP byte enables 68 Bus2IP_RdCE, // Bus to IP read chip enable 69 Bus2IP_WrCE, // Bus to IP write chip enable 70 IP2Bus_Data, // IP to Bus data bus 71 IP2Bus_RdAck, // IP to Bus read transfer acknowledgement 72 IP2Bus_WrAck, // IP to Bus write transfer acknowledgement 73 IP2Bus_Error // IP to Bus error response 74 // -- DO NOT EDIT ABOVE THIS LINE ------------------ 75 ); // user_logic 76 77 // -- ADD USER PARAMETERS BELOW THIS LINE ------------ 78 // --USER parameters added here 79 80 // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ 81 82 // -- DO NOT EDIT BELOW THIS LINE -------------------- 83 // -- Bus protocol parameters, do not add to or delete 84 parameter C_NUM_REG = 5; 85 parameter C_SLV_DWIDTH = 32; 86 // -- DO NOT EDIT ABOVE THIS LINE -------------------- 87 88 // -- ADD USER PORTS BELOW THIS LINE ----------------- 89 // --USER ports added here 90 input [7 : 0] SW_In; 91 output [7 : 0] LED_Out; 92 // -- ADD USER PORTS ABOVE THIS LINE ----------------- 93 94 // -- DO NOT EDIT BELOW THIS LINE -------------------- 95 // -- Bus protocol ports, do not add to or delete 96 input Bus2IP_Clk; 97 input Bus2IP_Resetn; 98 input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; 99 input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; 100 input [C_NUM_REG-1 : 0] Bus2IP_RdCE; 101 input [C_NUM_REG-1 : 0] Bus2IP_WrCE; 102 output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; 103 output IP2Bus_RdAck; 104 output IP2Bus_WrAck; 105 output IP2Bus_Error; 106 // -- DO NOT EDIT ABOVE THIS LINE -------------------- 107 108 //---------------------------------------------------------------------------- 109 // Implementation 110 //---------------------------------------------------------------------------- 111 112 // --USER nets declarations added here, as needed for user logic 113 reg [7 : 0] LED_reg; 114 115 // Nets for user logic slave model s/w accessible register example 116 reg [C_SLV_DWIDTH-1 : 0] slv_reg0; 117 reg [C_SLV_DWIDTH-1 : 0] slv_reg1; 118 reg [C_SLV_DWIDTH-1 : 0] slv_reg2; 119 reg [C_SLV_DWIDTH-1 : 0] slv_reg3; 120 reg [C_SLV_DWIDTH-1 : 0] slv_reg4; 121 wire [4 : 0] slv_reg_write_sel; 122 wire [4 : 0] slv_reg_read_sel; 123 reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; 124 wire slv_read_ack; 125 wire slv_write_ack; 126 integer byte_index, bit_index; 127 128 // USER logic implementation added here 129 130 // ------------------------------------------------------ 131 // Example code to read/write user logic slave model s/w accessible registers 132 // 133 // Note: 134 // The example code presented here is to show you one way of reading/writing 135 // software accessible registers implemented in the user logic slave model. 136 // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond 137 // to one software accessible register by the top level template. For example, 138 // if you have four 32 bit software accessible registers in the user logic, 139 // you are basically operating on the following memory mapped registers: 140 // 141 // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register 142 // "1000" C_BASEADDR + 0x0 143 // "0100" C_BASEADDR + 0x4 144 // "0010" C_BASEADDR + 0x8 145 // "0001" C_BASEADDR + 0xC 146 // 147 // ------------------------------------------------------ 148 149 assign 150 slv_reg_write_sel = Bus2IP_WrCE[4:0], 151 slv_reg_read_sel = Bus2IP_RdCE[4:0], 152 slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4], 153 slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4]; 154 155 // implement slave model register(s) 156 always @( posedge Bus2IP_Clk ) 157 begin 158 159 if ( Bus2IP_Resetn == 1'b0 ) 160 begin 161 //slv_reg0 <= 0; 162 //slv_reg1 <= 0; 163 slv_reg2 <= 0; 164 slv_reg3 <= 0; 165 // slv_reg4 <= 0; 166 end 167 else 168 case ( slv_reg_write_sel ) 169 /* 5'b10000 : 170 for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) 171 if ( Bus2IP_BE[byte_index] == 1 ) 172 slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; */ 173 5'b01000 : 174 for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) 175 if ( Bus2IP_BE[byte_index] == 1 ) 176 slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 177 5'b00100 : 178 for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) 179 if ( Bus2IP_BE[byte_index] == 1 ) 180 slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 181 5'b00010 : 182 for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) 183 if ( Bus2IP_BE[byte_index] == 1 ) 184 slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 185 /* 5'b00001 : 186 for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) 187 if ( Bus2IP_BE[byte_index] == 1 ) 188 slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; */ 189 default : begin 190 slv_reg0 <= slv_reg0; 191 slv_reg1 <= slv_reg1; 192 slv_reg2 <= slv_reg2; 193 slv_reg3 <= slv_reg3; 194 slv_reg4 <= slv_reg4; 195 end 196 endcase 197 198 end // SLAVE_REG_WRITE_PROC 199 200 // implement slave model register read mux 201 always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 ) 202 begin 203 204 case ( slv_reg_read_sel ) 205 5'b10000 : slv_ip2bus_data <= slv_reg0; 206 5'b01000 : slv_ip2bus_data <= slv_reg1; 207 5'b00100 : slv_ip2bus_data <= slv_reg2; 208 5'b00010 : slv_ip2bus_data <= slv_reg3; 209 5'b00001 : slv_ip2bus_data <= slv_reg4; 210 default : slv_ip2bus_data <= 0; 211 endcase 212 213 end // SLAVE_REG_READ_PROC 214 215 // ------------------------------------------------------------ 216 // Example code to drive IP to Bus signals 217 // ------------------------------------------------------------ 218 219 always @(posedge Bus2IP_Clk) 220 begin 221 slv_reg0[7 : 0] <= SW_In[7 : 0]; 222 LED_reg <= slv_reg1[7 : 0]; 223 end 224 225 always @(posedge Bus2IP_Clk) 226 begin 227 case(slv_reg0[1 : 0]) 228 2'b01 : slv_reg4 <= slv_reg2 + slv_reg3; 229 2'b10 : slv_reg4 <= slv_reg2 - slv_reg3; 230 default : slv_reg4 <= 0; 231 endcase 232 end 233 234 assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; 235 assign IP2Bus_WrAck = slv_write_ack; 236 assign IP2Bus_RdAck = slv_read_ack; 237 assign IP2Bus_Error = 0; 238 239 assign LED_Out = LED_reg; 240 241 endmodule
其中代码slv_reg0~slv_reg4为IP核中申请的5个寄存器，在这里可以根据自己的需要对这个5个寄存器的作用进行分配，在这里完全是按照自己的意愿分配，本程序中，我将slv_reg0用来存储sw的值，slv_reg1用来表示led的信息，slv_reg2和slv_reg3用来进行操作数的存储，slv_reg4用来存储运算结果。
注意，由于在模块中sw为input故他的值不是从总线上进行读取的，slv_reg4存储运算结果，其值也不需要进行存储，故需要对源程序中的一些信息进行注释，即对case下的第一和最后一个选项进行注释，这个地方需要进行自己的判断
另外用户逻辑的加入在代码：
1 always @(posedge Bus2IP_Clk) 2 begin 3 slv_reg0[7 : 0] <= SW_In[7 : 0]; 4 LED_reg <= slv_reg1[7 : 0]; 5 end 6 7 always @(posedge Bus2IP_Clk) 8 begin 9 case(slv_reg0[1 : 0]) 10 2'b01 : slv_reg4 <= slv_reg2 + slv_reg3; 11 2'b10 : slv_reg4 <= slv_reg2 - slv_reg3; 12 default : slv_reg4 <= 0; 13 endcase 14 end
可以看出本工程中的逻辑比较简单，就是根据sw的值进行操作数的加减运算。
在完成用户逻辑后，还需要对IP核的端口进行配置，与IPIF相连接(我是这么理解的，可能会不对)
在目录pcoresmy_calc_v1_v1_00_ahdlvhdl下对文件my_calc_v1.vhd进行更改，代码如下：
1 ------------------------------------------------------------------------------ 2 -- my_calc_v1.vhd - entity/architecture pair 3 ------------------------------------------------------------------------------ 4 -- IMPORTANT: 5 -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. 6 -- 7 -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. 8 -- 9 -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW 10 -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION 11 -- OF THE USER_LOGIC ENTITY. 12 ------------------------------------------------------------------------------ 13 -- 14 -- *************************************************************************** 15 -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** 16 -- ** ** 17 -- ** Xilinx, Inc. ** 18 -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** 19 -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** 20 -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** 21 -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** 22 -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** 23 -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** 24 -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** 25 -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** 26 -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** 27 -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** 28 -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** 29 -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** 30 -- ** FOR A PARTICULAR PURPOSE. ** 31 -- ** ** 32 -- *************************************************************************** 33 -- 34 ------------------------------------------------------------------------------ 35 -- Filename: my_calc_v1.vhd 36 -- Version: 1.00.a 37 -- Description: Top level design, instantiates library components and user logic. 38 -- Date: Fri Jul 19 15:24:36 2013 (by Create and Import Peripheral Wizard) 39 -- VHDL Standard: VHDL'93 40 ------------------------------------------------------------------------------ 41 -- Naming Conventions: 42 -- active low signals: "*_n" 43 -- clock signals: "clk", "clk_div#", "clk_#x" 44 -- reset signals: "rst", "rst_n" 45 -- generics: "C_*" 46 -- user defined types: "*_TYPE" 47 -- state machine next state: "*_ns" 48 -- state machine current state: "*_cs" 49 -- combinatorial signals: "*_com" 50 -- pipelined or register delay signals: "*_d#" 51 -- counter signals: "*cnt*" 52 -- clock enable signals: "*_ce" 53 -- internal version of output port: "*_i" 54 -- device pins: "*_pin" 55 -- ports: "- Names begin with Uppercase" 56 -- processes: "*_PROCESS" 57 -- component instantiations: "<ENTITY_>I_<#|FUNC>" 58 ------------------------------------------------------------------------------ 59 60 library ieee; 61 use ieee.std_logic_1164.all; 62 use ieee.std_logic_arith.all; 63 use ieee.std_logic_unsigned.all; 64 65 library proc_common_v3_00_a; 66 use proc_common_v3_00_a.proc_common_pkg.all; 67 use proc_common_v3_00_a.ipif_pkg.all; 68 69 library axi_lite_ipif_v1_01_a; 70 use axi_lite_ipif_v1_01_a.axi_lite_ipif; 71 72 ------------------------------------------------------------------------------ 73 -- Entity section 74 ------------------------------------------------------------------------------ 75 -- Definition of Generics: 76 -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width 77 -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width 78 -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size 79 -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe 80 -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout 81 -- C_BASEADDR -- AXI4LITE slave: base address 82 -- C_HIGHADDR -- AXI4LITE slave: high address 83 -- C_FAMILY -- FPGA Family 84 -- C_NUM_REG -- Number of software accessible registers 85 -- C_NUM_MEM -- Number of address-ranges 86 -- C_SLV_AWIDTH -- Slave interface address bus width 87 -- C_SLV_DWIDTH -- Slave interface data bus width 88 -- 89 -- Definition of Ports: 90 -- S_AXI_ACLK -- AXI4LITE slave: Clock 91 -- S_AXI_ARESETN -- AXI4LITE slave: Reset 92 -- S_AXI_AWADDR -- AXI4LITE slave: Write address 93 -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid 94 -- S_AXI_WDATA -- AXI4LITE slave: Write data 95 -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe 96 -- S_AXI_WVALID -- AXI4LITE slave: Write data valid 97 -- S_AXI_BREADY -- AXI4LITE slave: Response ready 98 -- S_AXI_ARADDR -- AXI4LITE slave: Read address 99 -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid 100 -- S_AXI_RREADY -- AXI4LITE slave: Read data ready 101 -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready 102 -- S_AXI_RDATA -- AXI4LITE slave: Read data 103 -- S_AXI_RRESP -- AXI4LITE slave: Read data response 104 -- S_AXI_RVALID -- AXI4LITE slave: Read data valid 105 -- S_AXI_WREADY -- AXI4LITE slave: Write data ready 106 -- S_AXI_BRESP -- AXI4LITE slave: Response 107 -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid 108 -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready 109 ------------------------------------------------------------------------------ 110 111 entity my_calc_v1 is 112 generic 113 ( 114 -- ADD USER GENERICS BELOW THIS LINE --------------- 115 --USER generics added here 116 -- ADD USER GENERICS ABOVE THIS LINE --------------- 117 118 -- DO NOT EDIT BELOW THIS LINE --------------------- 119 -- Bus protocol parameters, do not add to or delete 120 C_S_AXI_DATA_WIDTH : integer := 32; 121 C_S_AXI_ADDR_WIDTH : integer := 32; 122 C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; 123 C_USE_WSTRB : integer := 0; 124 C_DPHASE_TIMEOUT : integer := 8; 125 C_BASEADDR : std_logic_vector := X"FFFFFFFF"; 126 C_HIGHADDR : std_logic_vector := X"00000000"; 127 C_FAMILY : string := "virtex6"; 128 C_NUM_REG : integer := 1; 129 C_NUM_MEM : integer := 1; 130 C_SLV_AWIDTH : integer := 32; 131 C_SLV_DWIDTH : integer := 32 132 -- DO NOT EDIT ABOVE THIS LINE --------------------- 133 ); 134 port 135 ( 136 -- ADD USER PORTS BELOW THIS LINE ------------------ 137 --USER ports added here 138 -- ADD USER PORTS ABOVE THIS LINE ------------------ 139 GPIO_LED_Out : out std_logic_vector(7 downto 0); 140 GPIO_SW_In : in std_logic_vector(7 downto 0); 141 -- DO NOT EDIT BELOW THIS LINE --------------------- 142 -- Bus protocol ports, do not add to or delete 143 S_AXI_ACLK : in std_logic; 144 S_AXI_ARESETN : in std_logic; 145 S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 146 S_AXI_AWVALID : in std_logic; 147 S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 148 S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); 149 S_AXI_WVALID : in std_logic; 150 S_AXI_BREADY : in std_logic; 151 S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 152 S_AXI_ARVALID : in std_logic; 153 S_AXI_RREADY : in std_logic; 154 S_AXI_ARREADY : out std_logic; 155 S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 156 S_AXI_RRESP : out std_logic_vector(1 downto 0); 157 S_AXI_RVALID : out std_logic; 158 S_AXI_WREADY : out std_logic; 159 S_AXI_BRESP : out std_logic_vector(1 downto 0); 160 S_AXI_BVALID : out std_logic; 161 S_AXI_AWREADY : out std_logic 162 -- DO NOT EDIT ABOVE THIS LINE --------------------- 163 ); 164 165 attribute MAX_FANOUT : string; 166 attribute SIGIS : string; 167 attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; 168 attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; 169 attribute SIGIS of S_AXI_ACLK : signal is "Clk"; 170 attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; 171 end entity my_calc_v1; 172 173 ------------------------------------------------------------------------------ 174 -- Architecture section 175 ------------------------------------------------------------------------------ 176 177 architecture IMP of my_calc_v1 is 178 179 constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; 180 181 constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; 182 183 constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); 184 constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; 185 constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; 186 187 constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := 188 ( 189 ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address 190 ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address 191 ); 192 193 constant USER_SLV_NUM_REG : integer := 5; 194 constant USER_NUM_REG : integer := USER_SLV_NUM_REG; 195 constant TOTAL_IPIF_CE : integer := USER_NUM_REG; 196 197 constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := 198 ( 199 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space 200 ); 201 202 ------------------------------------------ 203 -- Index for CS/CE 204 ------------------------------------------ 205 constant USER_SLV_CS_INDEX : integer := 0; 206 constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); 207 208 constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; 209 210 ------------------------------------------ 211 -- IP Interconnect (IPIC) signal declarations 212 ------------------------------------------ 213 signal ipif_Bus2IP_Clk : std_logic; 214 signal ipif_Bus2IP_Resetn : std_logic; 215 signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 216 signal ipif_Bus2IP_RNW : std_logic; 217 signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); 218 signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); 219 signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); 220 signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); 221 signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); 222 signal ipif_IP2Bus_WrAck : std_logic; 223 signal ipif_IP2Bus_RdAck : std_logic; 224 signal ipif_IP2Bus_Error : std_logic; 225 signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); 226 signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); 227 signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); 228 signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); 229 signal user_IP2Bus_RdAck : std_logic; 230 signal user_IP2Bus_WrAck : std_logic; 231 signal user_IP2Bus_Error : std_logic; 232 233 ------------------------------------------ 234 -- Component declaration for verilog user logic 235 ------------------------------------------ 236 component user_logic is 237 generic 238 ( 239 -- ADD USER GENERICS BELOW THIS LINE --------------- 240 --USER generics added here 241 -- ADD USER GENERICS ABOVE THIS LINE --------------- 242 243 -- DO NOT EDIT BELOW THIS LINE --------------------- 244 -- Bus protocol parameters, do not add to or delete 245 C_NUM_REG : integer := 5; 246 C_SLV_DWIDTH : integer := 32 247 -- DO NOT EDIT ABOVE THIS LINE --------------------- 248 ); 249 port 250 ( 251 -- ADD USER PORTS BELOW THIS LINE ------------------ 252 --USER ports added here 253 -- ADD USER PORTS ABOVE THIS LINE ------------------ 254 LED_Out :out std_logic_vector(7 downto 0); 255 SW_In :in std_logic_vector(7 downto 0); 256 -- DO NOT EDIT BELOW THIS LINE --------------------- 257 -- Bus protocol ports, do not add to or delete 258 Bus2IP_Clk : in std_logic; 259 Bus2IP_Resetn : in std_logic; 260 Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); 261 Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); 262 Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); 263 Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); 264 IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); 265 IP2Bus_RdAck : out std_logic; 266 IP2Bus_WrAck : out std_logic; 267 IP2Bus_Error : out std_logic 268 -- DO NOT EDIT ABOVE THIS LINE --------------------- 269 ); 270 end component user_logic; 271 272 begin 273 274 ------------------------------------------ 275 -- instantiate axi_lite_ipif 276 ------------------------------------------ 277 AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif 278 generic map 279 ( 280 C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, 281 C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, 282 C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, 283 C_USE_WSTRB => C_USE_WSTRB, 284 C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, 285 C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, 286 C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, 287 C_FAMILY => C_FAMILY 288 ) 289 port map 290 ( 291 S_AXI_ACLK => S_AXI_ACLK, 292 S_AXI_ARESETN => S_AXI_ARESETN, 293 S_AXI_AWADDR => S_AXI_AWADDR, 294 S_AXI_AWVALID => S_AXI_AWVALID, 295 S_AXI_WDATA => S_AXI_WDATA, 296 S_AXI_WSTRB => S_AXI_WSTRB, 297 S_AXI_WVALID => S_AXI_WVALID, 298 S_AXI_BREADY => S_AXI_BREADY, 299 S_AXI_ARADDR => S_AXI_ARADDR, 300 S_AXI_ARVALID => S_AXI_ARVALID, 301 S_AXI_RREADY => S_AXI_RREADY, 302 S_AXI_ARREADY => S_AXI_ARREADY, 303 S_AXI_RDATA => S_AXI_RDATA, 304 S_AXI_RRESP => S_AXI_RRESP, 305 S_AXI_RVALID => S_AXI_RVALID, 306 S_AXI_WREADY => S_AXI_WREADY, 307 S_AXI_BRESP => S_AXI_BRESP, 308 S_AXI_BVALID => S_AXI_BVALID, 309 S_AXI_AWREADY => S_AXI_AWREADY, 310 Bus2IP_Clk => ipif_Bus2IP_Clk, 311 Bus2IP_Resetn => ipif_Bus2IP_Resetn, 312 Bus2IP_Addr => ipif_Bus2IP_Addr, 313 Bus2IP_RNW => ipif_Bus2IP_RNW, 314 Bus2IP_BE => ipif_Bus2IP_BE, 315 Bus2IP_CS => ipif_Bus2IP_CS, 316 Bus2IP_RdCE => ipif_Bus2IP_RdCE, 317 Bus2IP_WrCE => ipif_Bus2IP_WrCE, 318 Bus2IP_Data => ipif_Bus2IP_Data, 319 IP2Bus_WrAck => ipif_IP2Bus_WrAck, 320 IP2Bus_RdAck => ipif_IP2Bus_RdAck, 321 IP2Bus_Error => ipif_IP2Bus_Error, 322 IP2Bus_Data => ipif_IP2Bus_Data 323 ); 324 325 ------------------------------------------ 326 -- instantiate User Logic 327 ------------------------------------------ 328 USER_LOGIC_I : component user_logic 329 generic map 330 ( 331 -- MAP USER GENERICS BELOW THIS LINE --------------- 332 --USER generics mapped here 333 -- MAP USER GENERICS ABOVE THIS LINE --------------- 334 335 C_NUM_REG => USER_NUM_REG, 336 C_SLV_DWIDTH => USER_SLV_DWIDTH 337 ) 338 port map 339 ( 340 -- MAP USER PORTS BELOW THIS LINE ------------------ 341 --USER ports mapped here 342 LED_Out => GPIO_LED_Out, 343 344 SW_In => GPIO_SW_In, 345 -- MAP USER PORTS ABOVE THIS LINE ------------------ 346 347 Bus2IP_Clk => ipif_Bus2IP_Clk, 348 Bus2IP_Resetn => ipif_Bus2IP_Resetn, 349 Bus2IP_Data => ipif_Bus2IP_Data, 350 Bus2IP_BE => ipif_Bus2IP_BE, 351 Bus2IP_RdCE => user_Bus2IP_RdCE, 352 Bus2IP_WrCE => user_Bus2IP_WrCE, 353 IP2Bus_Data => user_IP2Bus_Data, 354 IP2Bus_RdAck => user_IP2Bus_RdAck, 355 IP2Bus_WrAck => user_IP2Bus_WrAck, 356 IP2Bus_Error => user_IP2Bus_Error 357 ); 358 359 ------------------------------------------ 360 -- connect internal signals 361 ------------------------------------------ 362 ipif_IP2Bus_Data <= user_IP2Bus_Data; 363 ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; 364 ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; 365 ipif_IP2Bus_Error <= user_IP2Bus_Error; 366 367 user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); 368 user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); 369 370 end IMP;
这个里面的一些部分比较难理解，我只是按照我的想法进行解释，不一定正确
我理解的这个文件是对IP核这个实体进行的配置，其中包括的部分分别是，实体的信息，包括实体包含的寄存器，寄存器位宽，实体的对外端口等，其代码为：
1 entity my_calc_v1 is 2 generic 3 ( 4 -- ADD USER GENERICS BELOW THIS LINE --------------- 5 --USER generics added here 6 -- ADD USER GENERICS ABOVE THIS LINE --------------- 7 8 -- DO NOT EDIT BELOW THIS LINE --------------------- 9 -- Bus protocol parameters, do not add to or delete 10 C_S_AXI_DATA_WIDTH : integer := 32; 11 C_S_AXI_ADDR_WIDTH : integer := 32; 12 C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; 13 C_USE_WSTRB : integer := 0; 14 C_DPHASE_TIMEOUT : integer := 8; 15 C_BASEADDR : std_logic_vector := X"FFFFFFFF"; 16 C_HIGHADDR : std_logic_vector := X"00000000"; 17 C_FAMILY : string := "virtex6"; 18 C_NUM_REG : integer := 1; 19 C_NUM_MEM : integer := 1; 20 C_SLV_AWIDTH : integer := 32; 21 C_SLV_DWIDTH : integer := 32 22 -- DO NOT EDIT ABOVE THIS LINE --------------------- 23 ); 24 port 25 ( 26 -- ADD USER PORTS BELOW THIS LINE ------------------ 27 --USER ports added here 28 -- ADD USER PORTS ABOVE THIS LINE ------------------ 29 GPIO_LED_Out : out std_logic_vector(7 downto 0); 30 GPIO_SW_In : in std_logic_vector(7 downto 0); 31 -- DO NOT EDIT BELOW THIS LINE --------------------- 32 -- Bus protocol ports, do not add to or delete 33 S_AXI_ACLK : in std_logic; 34 S_AXI_ARESETN : in std_logic; 35 S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 36 S_AXI_AWVALID : in std_logic; 37 S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 38 S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); 39 S_AXI_WVALID : in std_logic; 40 S_AXI_BREADY : in std_logic; 41 S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 42 S_AXI_ARVALID : in std_logic; 43 S_AXI_RREADY : in std_logic; 44 S_AXI_ARREADY : out std_logic; 45 S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 46 S_AXI_RRESP : out std_logic_vector(1 downto 0); 47 S_AXI_RVALID : out std_logic; 48 S_AXI_WREADY : out std_logic; 49 S_AXI_BRESP : out std_logic_vector(1 downto 0); 50 S_AXI_BVALID : out std_logic; 51 S_AXI_AWREADY : out std_logic 52 -- DO NOT EDIT ABOVE THIS LINE --------------------- 53 );
在这里需要对实体添加自定义的对外接口，SW和LED
下面就是对IP核的实现进行描述，包括IP核的架构(也是图形界面配置的一部分)包含的用户逻辑和用户逻辑到对外端口的映射关系
1 component user_logic is 2 generic 3 ( 4 -- ADD USER GENERICS BELOW THIS LINE --------------- 5 --USER generics added here 6 -- ADD USER GENERICS ABOVE THIS LINE --------------- 7 8 -- DO NOT EDIT BELOW THIS LINE --------------------- 9 -- Bus protocol parameters, do not add to or delete 10 C_NUM_REG : integer := 5; 11 C_SLV_DWIDTH : integer := 32 12 -- DO NOT EDIT ABOVE THIS LINE --------------------- 13 ); 14 port 15 ( 16 -- ADD USER PORTS BELOW THIS LINE ------------------ 17 --USER ports added here 18 -- ADD USER PORTS ABOVE THIS LINE ------------------ 19 LED_Out :out std_logic_vector(7 downto 0); 20 SW_In :in std_logic_vector(7 downto 0); 21 -- DO NOT EDIT BELOW THIS LINE --------------------- 22 -- Bus protocol ports, do not add to or delete 23 Bus2IP_Clk : in std_logic; 24 Bus2IP_Resetn : in std_logic; 25 Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); 26 Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); 27 Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); 28 Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); 29 IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); 30 IP2Bus_RdAck : out std_logic; 31 IP2Bus_WrAck : out std_logic; 32 IP2Bus_Error : out std_logic 33 -- DO NOT EDIT ABOVE THIS LINE --------------------- 34 ); 35 end component user_logic;
这部分用户逻辑的描述，需要再其中加入自己添加的部分，由于在用户逻辑中添加了SW和LED的输入输出，因此在这部分中需要进行添加
最后是用户逻辑中的端口到IP核对外端口的映射，在map中进行了体现，代码如下
1 USER_LOGIC_I : component user_logic 2 generic map 3 ( 4 -- MAP USER GENERICS BELOW THIS LINE --------------- 5 --USER generics mapped here 6 -- MAP USER GENERICS ABOVE THIS LINE --------------- 7 8 C_NUM_REG => USER_NUM_REG, 9 C_SLV_DWIDTH => USER_SLV_DWIDTH 10 ) 11 port map 12 ( 13 -- MAP USER PORTS BELOW THIS LINE ------------------ 14 --USER ports mapped here 15 LED_Out => GPIO_LED_Out, 16 17 SW_In => GPIO_SW_In, 18 -- MAP USER PORTS ABOVE THIS LINE ------------------ 19 20 Bus2IP_Clk => ipif_Bus2IP_Clk, 21 Bus2IP_Resetn => ipif_Bus2IP_Resetn, 22 Bus2IP_Data => ipif_Bus2IP_Data, 23 Bus2IP_BE => ipif_Bus2IP_BE, 24 Bus2IP_RdCE => user_Bus2IP_RdCE, 25 Bus2IP_WrCE => user_Bus2IP_WrCE, 26 IP2Bus_Data => user_IP2Bus_Data, 27 IP2Bus_RdAck => user_IP2Bus_RdAck, 28 IP2Bus_WrAck => user_IP2Bus_WrAck, 29 IP2Bus_Error => user_IP2Bus_Error 30 );
在完成以上代码的书写后，就基本完成了IP的控制，下面就是将IP核添加到工程中去，在此双击用户的IP核即可添加，在添加完成后，会在Bus Interface中发现此IP核，而后在port中进行配置，在port的配置过程中我理解为，此部分为经过IPIF包装后IP核的对外端口，通过这些对外端口可以进行一些外设的连接，而后此IP核映射到PS端，当作一个外设进行同意编址，PS端可以直接对地址进行操作，就可以控制外设(如sw和led)
将GPIO_LED_Out和GPIO_SW_In配置为External Ports，这样我理解是利用External Ports就可以对外设进行连接，外设看到的端口名称为my_calc_v1_0_GPIO_LED_Out_pin,和my_calc_v1_0_GPIO_SW_In_pin。
进行完端口的配置后，就可以进行约束文件的建立，将端口映射到FPGA的具体引脚上，约束文件如下：
1 # 2 # pin constraints 3 # 4 # 5 NET "my_calc_v1_0_GPIO_LED_Out_pin[0]" LOC = T22; 6 NET "my_calc_v1_0_GPIO_LED_Out_pin[1]" LOC = T21; 7 NET "my_calc_v1_0_GPIO_LED_Out_pin[2]" LOC = U22; 8 NET "my_calc_v1_0_GPIO_LED_Out_pin[3]" LOC = U21; 9 NET "my_calc_v1_0_GPIO_LED_Out_pin[4]" LOC = V22; 10 NET "my_calc_v1_0_GPIO_LED_Out_pin[5]" LOC = W22; 11 NET "my_calc_v1_0_GPIO_LED_Out_pin[6]" LOC = U19; 12 NET "my_calc_v1_0_GPIO_LED_Out_pin[7]" LOC = U14; 13 14 NET "my_calc_v1_0_GPIO_LED_Out_pin[0]" IOSTANDARD = LVCMOS33; 15 NET "my_calc_v1_0_GPIO_LED_Out_pin[1]" IOSTANDARD = LVCMOS33; 16 NET "my_calc_v1_0_GPIO_LED_Out_pin[2]" IOSTANDARD = LVCMOS33; 17 NET "my_calc_v1_0_GPIO_LED_Out_pin[3]" IOSTANDARD = LVCMOS33; 18 NET "my_calc_v1_0_GPIO_LED_Out_pin[4]" IOSTANDARD = LVCMOS33; 19 NET "my_calc_v1_0_GPIO_LED_Out_pin[5]" IOSTANDARD = LVCMOS33; 20 NET "my_calc_v1_0_GPIO_LED_Out_pin[6]" IOSTANDARD = LVCMOS33; 21 NET "my_calc_v1_0_GPIO_LED_Out_pin[7]" IOSTANDARD = LVCMOS33; 22 23 NET "my_calc_v1_0_GPIO_SW_In_pin[0]" LOC = F22; 24 NET "my_calc_v1_0_GPIO_SW_In_pin[1]" LOC = G22; 25 NET "my_calc_v1_0_GPIO_SW_In_pin[2]" LOC = H22; 26 NET "my_calc_v1_0_GPIO_SW_In_pin[3]" LOC = F21; 27 NET "my_calc_v1_0_GPIO_SW_In_pin[4]" LOC = H19; 28 NET "my_calc_v1_0_GPIO_SW_In_pin[5]" LOC = H18; 29 NET "my_calc_v1_0_GPIO_SW_In_pin[6]" LOC = H17; 30 NET "my_calc_v1_0_GPIO_SW_In_pin[7]" LOC = M15; 31 32 33 NET "my_calc_v1_0_GPIO_SW_In_pin[0]" IOSTANDARD = LVCMOS33; 34 NET "my_calc_v1_0_GPIO_SW_In_pin[1]" IOSTANDARD = LVCMOS33; 35 NET "my_calc_v1_0_GPIO_SW_In_pin[2]" IOSTANDARD = LVCMOS33; 36 NET "my_calc_v1_0_GPIO_SW_In_pin[3]" IOSTANDARD = LVCMOS33; 37 NET "my_calc_v1_0_GPIO_SW_In_pin[4]" IOSTANDARD = LVCMOS33; 38 NET "my_calc_v1_0_GPIO_SW_In_pin[5]" IOSTANDARD = LVCMOS33; 39 NET "my_calc_v1_0_GPIO_SW_In_pin[6]" IOSTANDARD = LVCMOS33; 40 NET "my_calc_v1_0_GPIO_SW_In_pin[7]" IOSTANDARD = LVCMOS33; 41 # additional constraints 42 #
完成后，XPS端的配置就完成，点击Generate BitStream生成bit文件，成功后导出的SDK
在进入SDK后，我们可以在system.xml文件中可以看到建立的IP核搭建的PL部分被当作外设映射到PS端，映射地址为0x78c00000
在此后我们只需要根据C语言的知识，对此地址端进行编程即可，下面逻辑就不再展开叙述，具体代码如下，写的比较乱
1 /* 2 * Copyright (c) 2009 Xilinx, Inc. All rights reserved. 3 * 4 * Xilinx, Inc. 5 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 6 * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 7 * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 8 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 9 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 10 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 11 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 12 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 13 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 14 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 15 * AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 */ 18 19 /* 20 * helloworld.c: simple test application 21 */ 22 23 #include <stdio.h> 24 #include "platform.h" 25 #define SW (* (volatile unsigned int *) 0x78C00000) // 26 #define LED (* (volatile unsigned int *) 0x78C00004) // 27 #define ADD1 (* (volatile unsigned int *) 0x78C00008) // 第一个寄存器地址---加数一 28 #define ADD2 (* (volatile unsigned int *) 0x78C0000C) // 第二个寄存器地址---加数二 29 #define SUM (* (volatile unsigned int *) 0x78C00010) // 第三个寄存器地址---和 30 31 //void print(char *str); 32 33 int main() 34 { 35 init_platform(); 36 37 printf("Hello World "); 38 printf("Please input the first operator: "); 39 scanf("%d", &ADD1); 40 printf("Please second the first operator: "); 41 scanf("%d", &ADD2); 42 if(SW == 0x01) 43 { 44 printf("The result of ADD1 + ADD2 = %d ", SUM); 45 } 46 else if(SW == 0x02) 47 { 48 printf("The result of ADD1 - ADD2 = %d ", SUM); 49 } 50 LED = SUM; 51 52 return 0; 53 }
完成代码的编写后进行板子的配置，并进行程序的下载，结果运行良好，第一个自己动手做的工程终于完成了，好长时间了不容易啊
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