Verilog实现八选一功能

Verilog实现八选一附带源码

其实八选一就是基于四选一上的，只要大家增加变量，定义好变量类型并注意码代码时的规范就行了
具体的可以看一下源码，以及测试程序：
此为源码

module mux8_to_1 (out,i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0);
  output out;
  input i0,i1,i2,i3,i4,i5,i6,i7;
  input s2,s1,s0;
    reg out;

  always @(s2 or s1 or s0 or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
    begin
      
         case({s2,s1,s0})
         2'b000: out = i0;
         2'b001: out = i1;
         2'b010: out = i2;
         2'b011: out = i3;
         2'b100: out = i4;
         2'b101: out = i5;
         2'b110: out = i6;
         2'b111: out = i7;
         default: out = 1'bx;
         endcase

   end

endmodule

此为测试代码:

`include"mux8_to_1.v"
  module t;
    reg a0, a1, a2, a3, a4, a5, a6, a7, select1, select2, select3;
    reg clock;
    wire outw;
    
  initial
  
  begin
    a0=0;
    a1=0;
    a2=0;
    a3=0;
    a4=0;
    a5=0;
    a6=0;
    a7=0;
    select1=0;
    select2=0;
    select3=0;
    clock=0;
  end

    always #50 clock = ~clock;
    
    always @(posedge clock)
      begin
        #1 a0 = {$random}%2;
        #3 a1 = {$random}%2;
        #5 a2 = {$random}%2;
        #7 a3 = {$random}%2;
        #9 a4 = {$random}%2;
        #11 a5 = {$random}%2;
        #13 a6 = {$random}%2;
        #15 a7 = {$random}%2;
      end
    
    always #1000 select1 = {$random}%2;
    always #1000 select2 = {$random}%2;
    always #1000 select3 = {$random}%2;
    
    mux8_to_1 m(.out(outw),.i0(a0),.i1(a1),.i2(a2),.i3(a3),.i4(a4),.i5(a5),.i6(a6),.i7(a7),.s0(select1),.s1(select2),.s2(select3));
endmodule

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