fft_fft_control

这是第三个部分，该模块实现了对fft ip核数据的控制,source_valid是fft的数据有效标志位，当数据有效时，开始往ram里

写数据，但是写数据之前需要对原始数据处理一下，通过实际下班运行发现，FFT变化那之后存在直流分量，可以把开始

数据舍去，方便以后数据的运算。

/*-----------------------------------------------------------------------

Date                :        2017-XX-XX
Description            :        Design for fft_control.

-----------------------------------------------------------------------*/

module fft_control
(
    //global clock
    input                    clk,            //system clock
    input                    rst_n,             //sync reset
    
    //fft interface
    input                    source_sop,
    input                    source_valid,
    input            [11:0]    source_real,
    input            [11:0]    source_imag,
    
    //ram    interface
    output    reg        [10:0]    rd_ram,
    output            [10:0]    wr_ram,
    output                    wren,
    output            [9:0]    q_ram,
    output            [9:0]    data,
    output            [12:0]    q_sig //开根号之后的数据
); 


//--------------------------------
//Funtion :    数据处理           
wire        [23:0]        result_real;
wire        [23:0]        result_image;

mul_10    mul_real (
    .dataa ( source_real ),
    .result ( result_real )
    );
    
mul_10    mul_image (
    .dataa ( source_imag ),
    .result ( result_image )
    );

reg        [24:0]        result_add;

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        result_add <= 24'd0;
    else
        result_add <= result_real + result_image;
end

//wire    [12:0]        q_sig;
    
sqrt    sqrt_inst (
    .radical ( result_add ),
    .q ( q_sig )
    //.remainder ( remainder_sig )
    );

    
assign        data = q_sig[12:3];
//--------------------------------
//Funtion :   写地址
reg        [10:0]        wr_ram1;
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        wr_ram1 <= 11'd0;
    else if(wren)
        wr_ram1 <= wr_ram1 + 1'd1;
    else
        wr_ram1 <= 1'd0;
end
//消除开始的直流分量  
assign    wr_ram    = (wr_ram1 > 2'd3) ? wr_ram1 - 2'd3 : 1'b0;
 
  

ram_1024x2048     ram_isnt(
    .clock(clk),
    .data(data),
    .rdaddress(rd_ram),
    .wraddress(wr_ram),
    .wren(wren),
    .q(q_ram)
    );

assign        wren = source_valid;

endmodule