基于BASYS2的VHDL程序——分频和数码管静态显示程序

转载请注明出处：http://www.cnblogs.com/connorzx/p/3633860.html 

分频是基于计数器程序。由于FPGA的并行处理能力，根本不需要单片机式的中断指令，用起来很方便。

数码管是靠段选和片选控制的。即所有数目管公用一套八段LED选择端，每个管的亮灭靠片选控制。只要刷新频率够高，就能出现连续的效果。

代码如下：

 1 library IEEE;
 2 use IEEE.STD_LOGIC_1164.ALL;
 3 use IEEE.STD_LOGIC_ARITH.ALL;
 4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 5 
 6 
 7 entity digit_node is
 8     Port ( 
 9            clk : in  STD_LOGIC;
10               an :  out  STD_LOGIC_VECTOR (3 downto 0);
11            seg : out  STD_LOGIC_VECTOR (6 downto 0));
12               
13 end digit_node;
14 
15 architecture Behavioral of digit_node is
16 signal cnt:  INTEGER;
17 signal sclk: STD_LOGIC;
18 signal sw:STD_LOGIC_VECTOR (3 downto 0);
19 begin
20 an<="0000";
21 process(clk)
22 begin
23 if(clk'event and clk='1') then
24     if(cnt=10000000) then
25         cnt<=0;
26         sclk<=not sclk;
27     else
28         cnt<=cnt+1;
29     end if;
30 end if;
31 end process;
32 process(sclk)
33 begin
34 if(sclk'event and sclk='1') then
35     sw<=sw+1;
36 case sw is
37     when x"0"=>seg<=b"0000001";
38     when x"1"=>seg<=b"1001111";
39     when x"2"=>seg<=b"0010010";
40     when x"3"=>seg<=b"0000110";
41     when x"4"=>seg<=b"1001100";
42     when x"5"=>seg<=b"0100100";
43     when x"6"=>seg<=b"0100000";
44     when x"7"=>seg<=b"0001111";
45     when x"8"=>seg<=b"0000000";
46     when x"9"=>seg<=b"0000100";
47     when x"a"=>seg<=b"0001000";
48     when x"b"=>seg<=b"1100000";
49     when x"c"=>seg<=b"0110001";
50     when x"d"=>seg<=b"1000010";
51     when x"e"=>seg<=b"0110000";
52     when x"f"=>seg<=b"0111000";
53     when others=>seg<=b"0000001";
54 end case;
55 end if;
56 end process;
57 
58 end Behavioral;

约束文件如下：

NET "clk"   LOC="B8";
NET "an<0>" LOC="K14";
NET "an<1>" LOC="M13";
NET "an<2>" LOC="J12";
NET "an<3>" LOC="F12";
#NET "seg<7>" LOC="N13";
NET "seg<6>" LOC="L14";
NET "seg<5>" LOC="H12";
NET "seg<4>" LOC="N14";
NET "seg<3>" LOC="N11";
NET "seg<2>" LOC="P12";
NET "seg<1>" LOC="L13";
NET "seg<0>" LOC="M12";