| Step | Description |
|---|
| Interrupt request sent to CPU |
The CPU receives a maskable interrupt request. |
| Set corresponding IFR flag |
When the CPU detects a valid maskable interrupt request, it sets and
latches the corresponding flag in one of the interrupt flag registers (IFR0
or IFR1). This flag stays latched until the interrupt is acknowledged or until
the flag is cleared by software or by a DSP hardware reset. (See the
description of IFR0 and IFR1 in section 2.8.2.) |
| Interrupt enabled in IER? |
The CPU cannot acknowledge the interrupt unless the corresponding
enable bit is 1 in one of the interrupt enable registers (IER0 or IER1). (See
the description of IER0 and IER1 in section 2.8.3.) |
| INTM = 0? |
The CPU cannot acknowledge the interrupt unless the interrupt mode bit
(INTM) is 0. That is, interrupts must be globally enabled. (See the
description of INTM in section 2.10.2.8. |
| Branch to interrupt service routine |
The CPU follows the interrupt vector to the interrupt service routine. While
branching, the CPU performs the following actions:
It completes instructions that have already made it to the decode
phase of the pipeline. Other instructions are flushed from the pipeline.
It clears the corresponding flag in IFR0 or IFR1, to indicate that the
interrupt has been acknowledged.
It saves certain registers values automatically, to record important
mode and status information about the interrupted program sequence
(see the description of automatic context switching in section 4.4).
It creates a fresh context for the ISR by forcing INTM = 1 (globally
disables interrupts), DBGM = 1 (disables debug events), and
EALLOW = 0 (disables access to non-CPU emulation registers) |
| Execute interrupt service routine |
The CPU executes the interrupt service routine (ISR) that you have written
for the acknowledged interrupt. Some registers values were saved
automatically during the branch to the ISR. A return-from-interrupt
instruction at the end of your ISR forces an automatic context restore
operation (see the description of automatic context switching in
section 4.4) to restore these register values. If the ISR shares other
registers with the interrupted program sequence, the ISR must save
other register values at the beginning of the ISR and restore these values
before returning to the interrupted program sequence |
| Program continues |
If the interrupt request is not properly enabled, the CPU ignores the
request, and the program continues uninterrupted. If the interrupt is
properly enabled, its interrupt service routine is executed, and then the
program continues from the point where it was interrupted. |
