Makefile

example:

# not include multi-dir
TOOL_CHAIN = gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi-
CC = ${TOOL_CHAIN}gcc
AS = ${TOOL_CHAIN}as
AR = ${TOOL_CHAIN}ar
LD = ${TOOL_CHAIN}ld
OBJCOPY = ${TOOL_CHAIN}objcopy
OBJDUMP = ${TOOL_CHAIN}objdump
READELF = ${TOOL_CHAIN}readelf

C_FLAGS := -Wall -I/usr/include -O0 -std=c11 -mcpu=cortex-m4 -mthumb -fno-builtin
LD_FLAGS := -T xxx.lds

all: main.c hello.c
	echo "This is a makefile test"
	${CC} -o $@.elf $^ ${C_FLAGS} ${LD_FLAGS}
	${OBJCOPY} -O binary -S $@.elf $@.bin
	${OBJDUMP} -D -m arm $@.elf > $@.dis

clean:
	rm *.o all.* -fr

note:

${} and $() are the same meaning, they can be used to represent the variables
:= signifies instant equal
all signifies target, main.c hello.c are prerequiries
$@ signifies the target
$^ signifies all the prerequiries
$< signifies the first prerequiries