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  • 【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07I

    Chapter 7. Behavioral Modeling

    7.11 Exercises

    1. Declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement ( Hint: Use the forever loop).

    my answer:

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    2. Design a clock with time period = 40 and a duty cycle of 25% by using the always and initial statements. The value of clock at time = 0 should be initialized to 0.

    my answer:

    clip_image006

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    3. Given below is an initial block with blocking procedural assignments. At what simulation time is each statement executed? What are the intermediate and final values of a, b, c, d?

    clip_image010

    my answer:

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    4. Repeat exercise 3 if nonblocking procedural assignments were used.

    my answer:

    clip_image014

    5. What is the order of execution of statements in the following Verilog code? Is there any ambiguity in the order of execution? What are the final values of a,b,c,d?

    clip_image016

    my answer:

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    6. What is the final value of d in the following example? (Hint: See intra-assignment delays.)

    clip_image020

    my answer:

    clip_image022

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  • 原文地址:https://www.cnblogs.com/halflife/p/1986865.html
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