1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the MX6Q Sabre Lite2 Freescale board. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 #include <asm/arch/mx6.h> 26 27 /* High Level Configuration Options */ 28 #define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ 29 #define CONFIG_MXC 30 #define CONFIG_MX6Q 31 #define CONFIG_MX6Q_SABRESD 32 #define CONFIG_FLASH_HEADER 33 #define CONFIG_FLASH_HEADER_OFFSET 0x400 34 #define CONFIG_MX6_CLK32 32768 35 36 #define CONFIG_SKIP_RELOCATE_UBOOT 37 38 #define CONFIG_ARCH_CPU_INIT 39 #undef CONFIG_ARCH_MMU /* disable MMU first */ 40 #define CONFIG_L2_OFF /* disable L2 cache first*/ 41 42 #define CONFIG_MX6_HCLK_FREQ 24000000 43 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 #define CONFIG_SYS_64BIT_VSPRINTF 48 49 #define BOARD_LATE_INIT 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SERIAL_TAG 53 #define CONFIG_REVISION_TAG 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_MXC_GPIO 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 62 /* size in bytes reserved for initial data */ 63 #define CONFIG_SYS_GBL_DATA_SIZE 128 64 65 /* 66 * Hardware drivers 67 */ 68 #define CONFIG_MXC_UART 69 #define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_CONS_INDEX 1 74 #define CONFIG_BAUDRATE 115200 75 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 76 77 /*********************************************************** 78 * Command definition 79 ***********************************************************/ 80 81 #include <config_cmd_default.h> 82 83 #define CONFIG_CMD_PING 84 #define CONFIG_CMD_DHCP 85 #define CONFIG_CMD_MII 86 #define CONFIG_CMD_NET 87 #define CONFIG_NET_RETRY_COUNT 100 88 #define CONFIG_NET_MULTI 1 89 #define CONFIG_BOOTP_SUBNETMASK 90 #define CONFIG_BOOTP_GATEWAY 91 #define CONFIG_BOOTP_DNS 92 93 #define CONFIG_CMD_SPI 94 #define CONFIG_CMD_I2C 95 #define CONFIG_CMD_IMXOTP 96 97 /* Enable below configure when supporting nand */ 98 #define CONFIG_CMD_SF 99 #define CONFIG_CMD_MMC 100 #define CONFIG_CMD_ENV 101 #define CONFIG_CMD_REGUL 102 103 #define CONFIG_CMD_CLOCK 104 #define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ 105 106 /* #define CONFIG_CMD_SATA */ 107 #undef CONFIG_CMD_IMLS 108 109 #define CONFIG_CMD_IMX_DOWNLOAD_MODE 110 111 #define CONFIG_BOOTDELAY 3 112 113 #define CONFIG_PRIME "FEC0" 114 115 #define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ 116 #define CONFIG_RD_LOADADDR (0x1300000) 117 118 #define CONFIG_EXTRA_ENV_SETTINGS 119 "netdev=eth0 " 120 "ethprime=FEC0 " 121 "uboot=u-boot.bin " 122 "kernel=uImage " 123 "nfsroot=/opt/eldk/arm " 124 "bootargs_base=setenv bootargs console=ttymxc0,115200 " 125 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " 126 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " 127 "bootcmd_net=run bootargs_base bootargs_nfs; " 128 "tftpboot ${loadaddr} ${kernel}; bootm " 129 "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " 130 "root=/dev/mmcblk0p1 rootwait " 131 "bootcmd_mmc=run bootargs_base bootargs_mmc; " 132 "mmc dev 3; " 133 "mmc read ${loadaddr} 0x800 0x2000; bootm " 134 "bootcmd=run bootcmd_net " 135 136 137 #define CONFIG_ARP_TIMEOUT 200UL 138 139 /* 140 * Miscellaneous configurable options 141 */ 142 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 143 #define CONFIG_SYS_PROMPT "MX6Q SABRESD U-Boot > " 144 #define CONFIG_AUTO_COMPLETE 145 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 146 /* Print Buffer Size */ 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 148 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 149 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 150 151 #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ 152 #define CONFIG_SYS_MEMTEST_END 0x10010000 153 154 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 155 156 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 157 158 #define CONFIG_SYS_HZ 1000 159 160 #define CONFIG_CMDLINE_EDITING 161 162 #define CONFIG_FEC0_IOBASE ENET_BASE_ADDR 163 #define CONFIG_FEC0_PINMUX -1 164 #define CONFIG_FEC0_MIIBASE -1 165 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM 166 #define CONFIG_MXC_FEC 167 #define CONFIG_FEC0_PHY_ADDR 0xFF 168 #define CONFIG_DISCOVER_PHY 169 #define CONFIG_ETH_PRIME 170 #define CONFIG_RMII 171 #define CONFIG_CMD_MII 172 #define CONFIG_CMD_DHCP 173 #define CONFIG_CMD_PING 174 #define CONFIG_IPADDR 192.168.1.103 175 #define CONFIG_SERVERIP 192.168.1.101 176 #define CONFIG_NETMASK 255.255.255.0 177 178 /* 179 * OCOTP Configs 180 */ 181 #ifdef CONFIG_CMD_IMXOTP 182 #define CONFIG_IMX_OTP 183 #define IMX_OTP_BASE OCOTP_BASE_ADDR 184 #define IMX_OTP_ADDR_MAX 0x7F 185 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 186 #endif 187 188 /* 189 * I2C Configs 190 */ 191 #ifdef CONFIG_CMD_I2C 192 #define CONFIG_HARD_I2C 1 193 #define CONFIG_I2C_MXC 1 194 #define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR 195 #define CONFIG_SYS_I2C_SPEED 100000 196 #define CONFIG_SYS_I2C_SLAVE 0x8 197 #endif 198 199 /* 200 * SPI Configs 201 */ 202 #ifdef CONFIG_CMD_SF 203 #define CONFIG_FSL_SF 1 204 #define CONFIG_SPI_FLASH_IMX_M25PXX 1 205 #define CONFIG_SPI_FLASH_CS 0 206 #define CONFIG_IMX_ECSPI 207 #define IMX_CSPI_VER_2_3 1 208 #define MAX_SPI_BYTES (64 * 4) 209 #endif 210 211 /* Regulator Configs */ 212 #ifdef CONFIG_CMD_REGUL 213 #define CONFIG_ANATOP_REGULATOR 214 #define CONFIG_CORE_REGULATOR_NAME "vdd1p1" 215 #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1" 216 #endif 217 218 /* 219 * MMC Configs 220 */ 221 #ifdef CONFIG_CMD_MMC 222 #define CONFIG_MMC 223 #define CONFIG_GENERIC_MMC 224 #define CONFIG_IMX_MMC 225 #define CONFIG_SYS_FSL_USDHC_NUM 4 226 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 227 #define CONFIG_SYS_MMC_ENV_DEV 2 228 #define CONFIG_DOS_PARTITION 1 229 #define CONFIG_CMD_FAT 1 230 #define CONFIG_CMD_EXT2 1 231 232 /* detect whether SD1, 2, 3, or 4 is boot device */ 233 #define CONFIG_DYNAMIC_MMC_DEVNO 234 235 /* SD3 and SD4 are 8 bit */ 236 #define CONFIG_MMC_8BIT_PORTS 0xC 237 /* Setup target delay in DDR mode for each SD port */ 238 #define CONFIG_GET_DDR_TARGET_DELAY 239 #endif 240 241 /* 242 * SATA Configs 243 */ 244 #ifdef CONFIG_CMD_SATA 245 #define CONFIG_DWC_AHSATA 246 #define CONFIG_SYS_SATA_MAX_DEVICE 1 247 #define CONFIG_DWC_AHSATA_PORT_ID 0 248 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 249 #define CONFIG_LBA48 250 #define CONFIG_LIBATA 251 252 #define CONFIG_DOS_PARTITION 1 253 #define CONFIG_CMD_FAT 1 254 #define CONFIG_CMD_EXT2 1 255 #endif 256 257 /* 258 * GPMI Nand Configs 259 */ 260 /* #define CONFIG_CMD_NAND */ 261 262 #ifdef CONFIG_CMD_NAND 263 #define CONFIG_NAND_GPMI 264 #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK 265 #define CONFIG_GPMI_NFC_V2 266 267 #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR 268 #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR 269 270 #define NAND_MAX_CHIPS 8 271 #define CONFIG_SYS_NAND_BASE 0x40000000 272 #define CONFIG_SYS_MAX_NAND_DEVICE 1 273 274 /* NAND is the unique module invoke APBH-DMA */ 275 #define CONFIG_APBH_DMA 276 #define CONFIG_APBH_DMA_V2 277 #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR 278 #endif 279 280 /*----------------------------------------------------------------------- 281 * Stack sizes 282 * 283 * The stack sizes are set up in start.S using the settings below 284 */ 285 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 286 287 /*----------------------------------------------------------------------- 288 * Physical Memory Map 289 */ 290 #define CONFIG_NR_DRAM_BANKS 1 291 #define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR 292 #define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) 293 #define iomem_valid_addr(addr, size) 294 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 295 296 /*----------------------------------------------------------------------- 297 * FLASH and environment organization 298 */ 299 #define CONFIG_SYS_NO_FLASH 300 301 /* Monitor at beginning of flash */ 302 #define CONFIG_FSL_ENV_IN_MMC 303 /* #define CONFIG_FSL_ENV_IN_NAND */ 304 /* #define CONFIG_FSL_ENV_IN_SATA */ 305 306 #define CONFIG_ENV_SECT_SIZE (8 * 1024) 307 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 308 309 #if defined(CONFIG_FSL_ENV_IN_NAND) 310 #define CONFIG_ENV_IS_IN_NAND 1 311 #define CONFIG_ENV_OFFSET 0x100000 312 #elif defined(CONFIG_FSL_ENV_IN_MMC) 313 #define CONFIG_ENV_IS_IN_MMC 1 314 #define CONFIG_ENV_OFFSET (768 * 1024) 315 #elif defined(CONFIG_FSL_ENV_IN_SATA) 316 #define CONFIG_ENV_IS_IN_SATA 1 317 #define CONFIG_SATA_ENV_DEV 0 318 #define CONFIG_ENV_OFFSET (768 * 1024) 319 #elif defined(CONFIG_FSL_ENV_IN_SF) 320 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 321 #define CONFIG_ENV_SPI_CS 1 322 #define CONFIG_ENV_OFFSET (768 * 1024) 323 #else 324 #define CONFIG_ENV_IS_NOWHERE 1 325 #endif 326 327 #define CONFIG_SPLASH_SCREEN 328 #ifdef CONFIG_SPLASH_SCREEN 329 /* 330 * Framebuffer and LCD 331 */ 332 #define CONFIG_LCD 333 #define CONFIG_IPU_V3H 334 #define CONFIG_VIDEO_MX5 335 #define CONFIG_IPU_CLKRATE 260000000 336 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 337 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 338 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 339 #define LCD_BPP LCD_COLOR16 340 #define CONFIG_CMD_BMP 341 #define CONFIG_BMP_8BPP 342 #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) 343 #define CONFIG_SPLASH_SCREEN_ALIGN 344 #define CONFIG_SYS_WHITE_ON_BLACK 345 346 #define CONFIG_IMX_PWM 347 #define IMX_PWM1_BASE PWM1_BASE_ADDR 348 #define IMX_PWM2_BASE PWM2_BASE_ADDR 349 #endif 350 #endif /* __CONFIG_H */