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  • aes加密/解密(转载)

    这篇文章是转载的康奈尔大学ece5760课程里边的一个final project,讲的比较通俗易懂,所以转载过来。附件里边是工程文件,需要注意一点,在用modelsim仿真过程中会出现错误,提示非法引用memory,网上搜了一下是因为verilog还不支持数组引用,但是system verilog是支持的,而且modelsim也支持system verilog的仿真,那么就需要把.v扩展名改为.sv就可以了。

    Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm which can be used to protect electronic data. The main idea of this project is to demonstrate the acceleration that can be achieved in executing this computation intensive encryption/decryption algorithm on hardware. FPGAs with their highly parallel, reconfigurable architecture are best suited for this project. To achieve this, we plan to build an SoC system with a NIOS II softcore processor instantiated inside an Altera Cyclone IV FPGA. As an outcome of this project, we should be able to encrypt/decrypt a huge chunk of data read from an SD card. In addition, we expect the execution time to be much lower for the hardware implementation when compared to its software counterpart.

    The overall system design

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  • 原文地址:https://www.cnblogs.com/lianjiehere/p/4707883.html
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