1 1 // how do I get MUXF5/MUXF6. 2 2 // This implies eight to one multiplexing, so use a three bit select in the case statement. 3 3 // This following will produce the LUT4/MUXF5/MUXF6 logic: 4 4 5 5 module lut_test8(a, b, c, f, s); 6 6 input[3:0]a, b; 7 7 input[1:0]s; 8 8 input[1:0]f; 9 9 output c; 10 10 11 11 reg c; 12 12 13 13 always @(a or b or f or s) 14 14 case({s,f[1]}) 15 15 4'b000: c = !f[0] ? (a[0] & b[0]) : (a[0] | b[0]); 16 16 4'b010: c = !f[0] ? (a[1] & b[1]) : (a[1] | b[1]); 17 17 4'b100: c = !f[0] ? (a[2] & b[2]) : (a[2] | b[2]); 18 18 4'b110: c = !f[0] ? (a[3] & b[3]) : (a[3] | b[3]); 19 19 4'b001: c = !f[0] ? (a[0] ^ b[0]) : (a[0] & ~b[0]); 20 20 4'b011: c = !f[0] ? (a[1] ^ b[1]) : (a[1] & ~b[1]); 21 21 4'b101: c = !f[0] ? (a[2] ^ b[2]) : (a[2] & ~b[2]); 22 22 4'b111: c = !f[0] ? (a[3] ^ b[3]) : (a[3] & ~b[3]); 23 23 endcase 24 24 25 25 endmodule
1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 08:21:54 05/11/2012 6 -- Design Name: 7 -- Module Name: mux_8_to_1 - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Description: 12 -- 13 -- Dependencies: 14 -- 15 -- Revision: 16 -- Revision 0.01 - File Created 17 -- Additional Comments: 18 -- 19 ---------------------------------------------------------------------------------- 20 library IEEE; 21 use IEEE.STD_LOGIC_1164.all; 22 23 -- Uncomment the following library declaration if using 24 -- arithmetic functions with Signed or Unsigned values 25 --use IEEE.NUMERIC_STD.ALL; 26 27 -- Uncomment the following library declaration if instantiating 28 -- any Xilinx primitives in this code. 29 --library UNISIM; 30 --use UNISIM.VComponents.all; 31 32 entity mux_8_to_1 is 33 port ( 34 i_select : in std_logic_vector(2 downto 0); 35 i_input : in std_logic_vector(7 downto 0); 36 o_output : out std_logic); 37 end mux_8_to_1; 38 39 architecture Behavioral of mux_8_to_1 is 40 signal input0123 : std_logic; 41 signal input4567 : std_logic; 42 signal input01 : std_logic; 43 signal input23 : std_logic; 44 signal input45 : std_logic; 45 signal input67 : std_logic; 46 47 begin 48 49 -- input01 <= i_input(1) when i_select(0) = '1' else i_input(0); 50 -- input23 <= i_input(3) when i_select(0) = '1' else i_input(2); 51 -- input45 <= i_input(4) when i_select(0) = '1' else i_input(4); 52 -- input67 <= i_input(5) when i_select(0) = '1' else i_input(6); 53 -- 54 -- input4567 <= input67 when i_select(1) = '1' else input45; 55 -- input0123 <= input23 when i_select(1) = '1' else input01; 56 -- 57 -- o_output <= input4567 when i_select(2) = '1' else input0123; 58 59 process ( i_input, i_select ) 60 begin 61 case i_select (2 downto 0) is 62 when "000" => o_output <= i_input (0); 63 when "001" => o_output <= i_input (1); 64 when "010" => o_output <= i_input (2); 65 when "011" => o_output <= i_input (3); 66 when "100" => o_output <= i_input (4); 67 when "101" => o_output <= i_input (5); 68 when "110" => o_output <= i_input (6); 69 when "111" => o_output <= i_input (7); 70 when others => o_output <= 'X'; 71 end case; 72 end process; 73 74 end Behavioral;