modesim测试语句

0:    fork  Reg1 = 4'd2; Reg2 <= Reg1; i <= i + 1'b1; join
0:    fork  Reg2 <= Reg1;Reg1 = 4'd2; i <= i + 1'b1; join
0:    begin  Reg1 = 4'd2; Reg2 <= Reg1; i <= i + 1'b1; end
0:    begin  Reg2 <= Reg1;Reg1 = 4'd2; i <= i + 1'b1; end

均是按顺序执行？

1. always @ ( 铭感区域 ) Reg1 <= ~Reg1;
2. always @ ( * ) Reg1 = ~Reg1;
3. always Reg1 <= ~Reg1;
4. forever Reg1<= ~Reg1;

3.4为验证语法，综合无法实现 

过程控制：

`timescale 1 ps/ 1 ps
module exp09_simulation();
    
    /*********************/ // environment signal
    reg CLK, RSTn;
    
    initial                                                
        begin                                                      
        CLK = 1; RSTn = 0; #10; RSTn = 1; 
         end   
          always #5 CLK = ~CLK;     
      /********************/

    initial $monitor($time,,,"clk=%b i=%d j=%d",CLK, i, j);

    reg [2:0]i;
    reg [2:0]j;
    reg [3:0]Reg1;
    
    always @ ( posedge CLK or negedge RSTn )
        if( !RSTn ) 
            begin 
                i <= 3'd0; 
                Reg1 <= 4'd0; 
            end
        else 
            case( i )
            
                0:
                begin Reg1 <= 4'd1; i <= i + 1'b1; end
                
                1:
                begin Reg1 <= 4'd2; i <= i + 1'b1; end
                
                2:
                if( j == 3) i <= i + 1'b1;
                
                3:
                begin Reg1 <= 4'd3; i <= i + 1'b1; end
                
            endcase
    
    /********************/    
    
    reg [3:0]Reg2;
    
    always @ ( posedge CLK or negedge RSTn )
        if( !RSTn ) 
            begin 
                j <= 3'd0; 
                Reg2 <= 4'd0; 
            end
        else 
            case( j )
            
                0:
                if( i == 2 ) j <= j + 1'b1;
                
                1:
                begin Reg2 <= 4'd1; j <= j + 1'b1; end
                
                2:
                j <= j;
                
                3:
                begin Reg2 <= 4'd2; j <= j + 1'b1; end    
                
            endcase
    
    /********************/    
    
endmodule