FIR滤波器设计流程 fpga （定点）
流程：
1.计算出FIR脉冲响应
2.量化
定点总位数：G+输入位宽 
f[k]脉冲响应
防止动态范围溢出 加减乘除···
3.仿真，代数分析，看量化后的设计是否符合要求
module fir_srg //----> Interface
(
input clk,
input [7:0] x,
output reg [7:0] y
);
// Tapped delay line array of bytes
reg [7:0] tap [0:3];
// For bit access use single vectors in Verilog integer I;
always @(posedge clk) //----> Behavioral style
begin : p1
// Compute output y with the filter coefficients weight.
// The coefficients are [-1 3.75 3.75 -1].
// Multiplication and division for Altera MaxPlusII can
// be done in Verilog 2001 with signed shifts ! 时域相乘 累加 响应
y <= (tap[1] <<< 1) + tap[1] + (tap[1] >>> 1) - tap[0]
+ ( tap[1] >>> 2) + (tap[2] <<< 1) + tap[2]
+ (tap[2] >>> 1) + (tap[2] >>> 2) - tap[3];
for (I=3; I>0; I=I-1) begin
tap[I] <= tap[I-1]; // Tapped delay line: shift one
end
tap[0] <= x; // Input in register 0
end
endmodule