1 // ********************************************************************* // 2 // Filename : powersequnce.v // 3 // Projects : powersequnce // 4 // Author : liuqiang // 5 // Date : 2013-04-16 // 6 // Version : 1.0 // 7 // Company : JuSha // 8 // ********************************************************************* // 9 10 `timescale 1ns/1ns 11 //generate powersequnce1,powersequnce2,clk_10 12 //powersequnce1: _______________ ____________________ 13 // _____| |_________________________| 14 // 1ms 3ms 5ms 4ms 15 //powersequnce2: __________ _________________________ 16 // ____________________| |_______________| 17 // 40us 20us 30us 50us 18 //freq=50M,Time=20ns;Time=1us,freq=1M;Time=1ms,freq=1k 19 //为了最大优化资源，我们选择500分频，即10us为周期的脉冲 20 module powersequnce( 21 input clk_50,rst_n, 22 output clk_10, 23 output reg sequnce1, 24 output reg sequnce2 25 ); 26 27 parameter PERIORD = 500; 28 29 reg clk_out1,clk_out2; 30 reg[8:0] cnt1; 31 reg[10:0] sequnce1_cnt; 32 reg[3:0] sequnce2_cnt; 33 //持续计数 34 always@(posedge clk_50 or negedge rst_n) 35 if(!rst_n) 36 cnt1<=0; 37 else 38 if(cnt1==PERIORD/2-1) 39 cnt1<=0; 40 else 41 cnt1<=cnt1+1'b1; 42 43 reg clk_locked ; 44 always@(posedge clk_50 or negedge rst_n) 45 if(!rst_n) begin 46 clk_out1<= 1'b0; 47 clk_locked <= 1'b0; 48 end 49 else 50 if(cnt1==PERIORD/2-1) begin 51 clk_out1<= ! clk_out1 ; 52 clk_locked <= 1'b1; 53 end 54 else begin 55 clk_out1<=clk_out1 ; 56 clk_locked <= clk_locked; 57 end 58 59 //初始时不稳定，generate一个delay 60 wire rst_n1 = rst_n & clk_locked; 61 //generate powersequnce1 62 always@(posedge clk_out1 or negedge rst_n1) 63 if(!rst_n) 64 sequnce1_cnt <= 1'b0; 65 else begin 66 if(sequnce1_cnt== 1300-1) //sequnce1=1ms+5ms+3ms+4ms=13ms=1300x10us 67 sequnce1_cnt <= 0 ; 68 else 69 sequnce1_cnt <= sequnce1_cnt + 1'b1; 70 end 71 72 always@(posedge clk_out1 or negedge rst_n1) 73 if(!rst_n1) begin 74 sequnce1 <= 1'B0; 75 // sequnce2 <= 1'b0; 76 end 77 else begin 78 if(sequnce1_cnt== 100-1) 79 sequnce1 <= 1'b1 ; 80 else if (sequnce1_cnt== 400-1) 81 sequnce1 <= 1'b0; 82 else if (sequnce1_cnt== 900-1) 83 sequnce1<= 1'b1; 84 else if (sequnce1_cnt== 1300-1) 85 sequnce1<= 1'b0; 86 else 87 sequnce1 <= sequnce1; 88 89 if(sequnce1_cnt[3:0]== 4-1) 90 sequnce2 <= 1'b1 ; 91 else if (sequnce1_cnt[3:0]== 6-1) 92 sequnce2 <= 1'b0; 93 else if (sequnce1_cnt[3:0]== 9-1) 94 sequnce2<= 1'b1; 95 else if (sequnce1_cnt[3:0]== 14-1) 96 sequnce2<= 1'b0; 97 else 98 sequnce2 <= sequnce2; 99 end 100 101 /* //generate powersequnce2 102 always@(posedge clk_out1 or negedge rst_n1) 103 if(!rst_n) 104 sequnce2_cnt <= 1'b0; 105 else begin 106 if(sequnce2_cnt== 14-1) //sequnce1=40us+20us+30us+50us=14x10us 107 sequnce2_cnt <= 0 ; 108 else 109 sequnce2_cnt <= sequnce2_cnt + 1'b1; 110 end 111 always@(posedge clk_out1 or negedge rst_n1) 112 if(!rst_n1) begin 113 sequnce2 <= 1'B0; 114 // sequnce2 <= 1'b0; 115 end 116 else begin 117 if(sequnce2_cnt== 4-1) 118 sequnce2 <= 1'b1 ; 119 else if (sequnce2_cnt== 6-1) 120 sequnce2 <= 1'b0; 121 else if (sequnce2_cnt==9-1) 122 sequnce2<= 1'b1; 123 else if (sequnce2_cnt== 14-1) 124 sequnce2<= 1'b0; 125 else 126 sequnce2 <= sequnce2; 127 end */ 128 endmodule
1 `timescale 1ns/1ns 2 3 module powersequnce_tb; 4 5 reg clk_50,rst_n; 6 wire clk_10; 7 8 powersequnce powersequnce_tb( 9 .clk_50(clk_50), 10 .rst_n(rst_n), 11 //.clk_10(clk_10), 12 //.clk_1(clk_1), 13 .sequnce1(sequnce1), 14 .sequnce2(sequnce2) 15 ); 16 17 initial begin //generator clk_50 18 clk_50=0; 19 forever #10 clk_50=~clk_50; 20 end 21 22 initial begin //generator rst_n 23 rst_n=0; 24 #5 rst_n=0; 25 #100 rst_n=1; 26 end 27 28 29 endmodule 30 31
PS:在testbench中进行clk上升沿和下降沿采样的时间要考虑rst_n的generate时间，是否可以采样到