在电源上叠加一个脉冲信号，模拟一个干扰信号

原理：通过MCU控制开关K1通断，产生尖脉冲叠加到电源上，电位器对脉冲幅度、波形进

行调节。通过按键(S1/2/3)选择输出不同频率，及占空比可调，使干扰测试更加灵活。

这里的MCU用CPLD代替，因有现成的CPLD板子，故用的Verilog写的，代码如下：

module Counter(
                rst_n,
                clk_in,
                key_add,
                key_sub,
                key_mode,
                oe,
                clk_out
                );
input         clk_in;
input         rst_n;
input         key_add;
input        key_sub;
input        key_mode;
output        oe;
output        clk_out;

parameter     T22MS = 20'd667_999;
parameter     T33US = 10'd999;   //33us
parameter     T11US = 9'd332;    //11us

/*************************************************************/
// key detect
reg[2:0] key_add_clk;
always @(posedge clk_in or negedge rst_n)
   if(!rst_n) key_add_clk <= 3'b111;
   else key_add_clk <= {key_mode,key_add,key_sub};
     
reg[2:0] key_add_clk_r;
always @(posedge clk_in or negedge rst_n)
    if(!rst_n) key_add_clk_r <= 3'b111;
    else key_add_clk_r <= key_add_clk;
      
wire[2:0] key_clk_en;
assign key_clk_en = key_add_clk_r & (~key_add_clk);

//按键消抖
reg[19:0] cnt;                                                   
always @(posedge clk_in or negedge rst_n)                           
    if(!rst_n) cnt <= 20'd0;                                     
    else if(key_clk_en) cnt <= 20'd0;                                
    else cnt <= cnt + 1'b1;
                                       
//每隔20ms就取按键上的值                                     
reg[2:0] pin_status;                                             
always @(posedge clk_in or negedge rst_n)                           
    if(!rst_n) pin_status <= 3'b111;                             
    else if(cnt == T22MS) pin_status <= {key_mode,key_add,key_sub};
                                                                 
reg[2:0] pin_status_r;            
always @(posedge clk_in or negedge rst_n)                           
    if(!rst_n) pin_status_r <= 3'b111;              
    else pin_status_r <= pin_status;    
                          
//前20MS的值与后20MS的值                                         
wire[2:0]  pin_status_ctrl;                                      
assign pin_status_ctrl = pin_status_r & (~pin_status);  
/*************************************************************/
       
/*************************************************************/
//mode selct  
//CS = 0,regulating frequency 
//CS = 1,regulating pulse 
reg cs;
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        cs <= 1'b0;
    else if(pin_status_ctrl[2])
        cs <= ~cs;
    else 
        cs <= cs;
/*************************************************************/

/*************************************************************/
//regulating frequency
reg[11:0] buff;  //max = 135us
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        buff <= T11US;
    else if(~cs)
    begin
        if(pin_status_ctrl[1])
        begin
            if((buff < 12'd4095)&&(buff >= T11US))
            begin
                buff <= buff + 7'd100;  //3us
                if(buff >=12'd4095)
                    buff <= T11US;
            end
            else
                buff <= T11US;
        end
        else if(pin_status_ctrl[0])
        begin
            if((buff > T11US) && (buff <=12'd4095))
            begin
                buff <= buff - 7'd100;
                if(buff <= T11US)
                    buff <= 12'd4095;
            end
            else 
                buff <= 12'd4095;
        end
    end
    
reg[11:0]     cnt1;
reg         clk_tmp;
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        begin
            cnt1 <= 0;
            clk_tmp <= 1'b0;
        end
    else if(~cs)
    begin
        if(cnt1 == buff)
        begin
            cnt1 <= 0;
            clk_tmp <= ~clk_tmp;
        end
        else
            cnt1 <= cnt1 + 1'b1;
    end
/*************************************************************/
/*************************************************************/
//regulating pulse width (duty ratio)
reg[31:0] number;
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        number <= buff;//32'd10;
    else if(cs)
    begin
        if(number == period)
            number<= 32'd10;
        else if(pin_status_ctrl[1])
        begin
            number <= number + 4'd10;//1'b1;
            if(number >= period)
                number <= 32'd10;
        end
        else if(pin_status_ctrl[0])
        begin
            number <= number - 4'd10;//1'b1
            if(number <= 32'd10)
                number <= period - 1'b1;
        end
        else 
            number <= number;
    end
    else
        number <= buff;
        
reg[31:0]     cnt2;
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        cnt2 <= 32'h0000_0000;
    else if(cs)
    begin
        if(cnt2 == period)
            cnt2 <= 32'h0000_0000;
        else
            cnt2 <= cnt2 + 1'b1;
    end
    else
        cnt2 <= 32'h0000_0000;

reg         pwm_tmp;            
always@(posedge clk_in or negedge rst_n)
    if(~rst_n)
        pwm_tmp <= 1'b0;
    else if(cs)
    begin
        case(cnt2)
        32'd0:        pwm_tmp <= 1'b1;
        number:        pwm_tmp <= 1'b0;
        period:     pwm_tmp <= 1'b1;
        default:    pwm_tmp <= pwm_tmp;
        endcase
    end
/*************************************************************/
/*************************************************************/
wire[31:0]     period;
assign         period = buff<<1;  //period = buff x 2
assign         oe = 1'b0;
assign         clk_out = cs ? pwm_tmp:clk_tmp;
/*************************************************************/
endmodule

该代码功能输出的频率可调，占空比也可调。