systemverilog中堵塞和非堵塞事件以及同步

一、SV中非堵塞事件

module test;

event ev1, ev2;

//belong to logic function part
always@(ev1)
$display("ev1 triggered at %0ts", $time);

initial wait(ev2.triggered)
$display("ev2 triggered at %0ts", $time);

//belong to stimulus
initial begin
->> #5 ev1; //"->>": non-blocking event, delay 5 cycle triggering the event
end

initial begin
->> @(ev1) ev2;       //event ev1 and ev2 will triggered simutaneous,but ev1 is earlier.
end

endmodule

//Makefile
comp:
vcs -sverilog Synchronous multi-events.sv -l comp.log
run:
./simv -l run.log
clean:
m -rf csrc simv* *.log

//run.log
ev1 triggered at 5s

ev2 triggered at 5s

//--------------------------------------------------------------------------------------------------------------

二、SV中堵塞事件

program p;

event e1, e2;

initial begin

$display("@%0t: 1: before trigger", $time);

->e1; //首先这样的事件是一个零宽度的脉冲

@e2;

$display("@%0t: 1: after trigger", $time);

end

initial begin

$display("@%0t: 2: before trigger", $time);

->e2;

@e1;

$display("@%0t: 2: after trigger", $time);

end

endprogram

//Makefile
comp:
vcs -sverilog *..sv -l comp.log
run:
./simv -l run.log
clean:
m -rf csrc simv* *.log

//run.log
@0: 1: before trigger

@0: 2: before trigger

@0: 1: after trigger

#解释：

两个initial块同一时刻运行，但即便是在同一时刻运行也有先后顺序。依照书写顺序从上到下运行（试验过两个initial块前后位置调换，结果恰好相反）。即，同一时刻事件e1先运行完，在@e2处等待，同一时候呢，事件e2也被触发。尽管在同一时刻。但因为e1早于e2被触发，所以，兴许e2的触发是@e2继续运行，但当到@e1时，因为此时事件e1已经被触发，程序会堵在@e1处。呈现如上log中的结果。