校招Verilog——译码器

一、2-4译码器

module Decode_2_4
(
    input           [1:0]   indata,
    input                   enable_n,
    output reg      [3:0]   outdata
);

always @(*)begin
    if(enable_n == 1'b1)
        outdata = 4'b1111;
    else begin
        case(indata)
            2'b00: outdata = 4'b1110;
            2'b01: outdata = 4'b1101;
            2'b10: outdata = 4'b1011;
            2'b11: outdata = 4'b0111;
        endcase
    end
end

endmodule

二、BCD译码器

module Decode_4_10
(
    input       [3:0] indata,
    output reg  [9:0] outdata
);

always @(*)begin
    case(indata)
        4'b0000: outdata = 10'b1111_1111_10;
        4'b0001: outdata = 10'b1111_1111_01;
        4'b0010: outdata = 10'b1111_1110_11;
        4'b0011: outdata = 10'b1111_1101_11;
        4'b0100: outdata = 10'b1111_1011_11;
        4'b0101: outdata = 10'b1111_0111_11;
        4'b0110: outdata = 10'b1110_1111_11;
        4'b0111: outdata = 10'b1101_1111_11;
        4'b1000: outdata = 10'b1011_1111_11;
        4'b1001: outdata = 10'b0111_1111_11;
        default: outdata = 10'b1111_1111_11;
    endcase
end

endmodule