【iCore1S 双核心板_FPGA】例程十二：基于单口RAM的ARM+FPGA数据存取实验

实验现象：

核心代码：

module single_port_ram(
                                    input CLK_12M,
                                    input WR,
                                    input RD,
                                    input CS0,
                                    inout [15:0]DB,
                                    input [24:16]A,
                                    output FPGA_LEDR,
                                    output FPGA_LEDG,
                                    output FPGA_LEDB
                                );
//----------------------------pll-------------------------------//
    /*实例化MY_PLL模块，输出48M时钟*/
    my_pll    u1(
                    .inclk0(CLK_12M),
                    .c0(PLL_48M)
                    );

//---------------------------rst_n----------------------------//                            
    /*复位信号，10个周期后rst_n置1*/    
    reg [3:0]cnt_rst=4'd0;
    reg rst_n;
    
    always@(posedge CLK_12M)
        begin
            if(cnt_rst==4'd10)
                begin
                    rst_n <= 1'd1;
                    cnt_rst <= 4'd10;
                end
            else     cnt_rst <= cnt_rst + 1'd1;
        end
        
//-------------------------fsmc-----------------------------//
    wire rd =(CS0|RD);//    提取读信号
    wire wr =(CS0|WR);//    提取写信号
    reg wr_clk1,wr_clk2;
    
    always@(posedge PLL_48M or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    wr_clk1 <= 1'd1;
                    wr_clk2 <= 1'd1;
                end 
            else {wr_clk2,wr_clk1} <= {wr_clk1,wr};
        end 
    
    wire clk = (!wr_clk2|!rd);  //将读写信号转化为时钟信号
    assign DB = !rd?DB_OUT :16'hzzzz;
    
//---------------------------ram-------------------------------//
    /*实例化ram块*/
    wire [15:0]DB_OUT;
    
    my_ram u2(
                    .address(A),
                    .clock(clk),
                    .data(DB),
                    .wren(!wr),
                    .rden(!rd),
                    .q(DB_OUT)
                );
                
//--------------------------led----------------------------//    

    assign FPGA_LEDR = 1'd1;
    assign FPGA_LEDG = 1'd0;
    assign FPGA_LEDB = 1'd1;
    
//-----------------------endmodule-------------------------//
endmodule     

实验方法及指导书:

链接：http://pan.baidu.com/s/1jIBXsSu 密码：38q7