【iCore4 双核心板_FPGA】例程十七：基于FIFO的ARM+FPGA数据存取实验

实验现象：

核心代码：

int main(void)
{

  /* USER CODE BEGIN 1 */
    int i;
    int fsmc_read_data;
    char error_flag = 0;
    char receive_data[50];
    char buffer[15];
    char *p;
  /* USER CODE END 1 */

  /* MCU Configuration----------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_USART6_UART_Init();
  MX_FMC_Init();

  /* USER CODE BEGIN 2 */
    usart6.initialize(115200);
    usart6.printf("Hello,I am iCore4!
");
    LED_GREEN_ON;
  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
  /* USER CODE END WHILE */

  /* USER CODE BEGIN 3 */
        if(usart6.receive_ok_flag == 1){
            usart6.receive_ok_flag = 0;
            memset(receive_data,0,sizeof(receive_data));
            memset(buffer,0,sizeof(buffer));
            for(i = 0;i < 30;i ++){
                receive_data[i] = usart6.receive_buffer[i];
            }
            p = receive_data;
            i = 0;
            while(*p != '
'){                                    //»ñÈ¡²Ù×÷ÃüÁî
                buffer[i++] = *p++;
                if(i > sizeof(buffer))i = 0;
            }
            for(i = 0;i < sizeof(buffer);i++){//½«ÃüÁîת»¯ÎªÐ¡Ð´×Ö·û
                buffer[i] = tolower(buffer[i]);
            }

            if(memcmp(buffer,"write_fifo",strlen("write_fifo")) == 0){//Ö´ÐÐдFifo
                error_flag = 0;
                usart6.printf("Data In Fifo:");
                for(i = 0;;i++){
                    fpga_write(0,i);
                    usart6.printf("%d ",i);
                    if(FIFO_FULL){    
                        fpga_write(0,i+1);
                        usart6.printf("%d ",i+1);                        
                        usart6.printf("  
Fifo is Full!
   Data Out Fifo:");
                        for(i = 0;i < 256;i++){                              //¿ªÊ¼¶ÁÈ¡256¸öÊý¾Ý
                            fsmc_read_data = fpga_read(0);
                            usart6.printf("%d ",fsmc_read_data);        //¶ÁÈ¡Öµ·¢ËÍÖÁ´®¿Ú    
                        }
                        break;
                    }        
                }
            }else{
                error_flag = 1;
            }
            
            if(error_flag){
                LED_RED_ON;
                LED_GREEN_OFF;
                usart6.printf("Bad Command!
");
            }else{
                LED_RED_OFF;
                LED_GREEN_ON;
            }
        }
  }
  /* USER CODE END 3 */

}

module fifo_wr_rd(
    input clk_25m,
    input rst_n,
    input wrn,
    input rdn,
    input cs0,
    input nadv,
    input [22:16]ab,
    inout [15:0]db,
    output fifo_full_flag,
    output led_red,
    output led_green,
    output led_blue
);

pll u1(
    .inclk0(clk_25m),
    .c0(clk_150m)
);

wire [15:0]data_out;
my_fifo u2(
    .data(data_in),
    .wrreq(1'd1),
    .wrclk(wr2),
    .rdreq(1'd1),
    .rdclk(!rd),
    .wrfull(fifo_full_flag),
    .q(data_out)
);

reg [15:0]data_in;
always@(posedge wrn or negedge rst_n)
    if(!rst_n)
        data_in <= 16'd0;
    else
        data_in <= db;
        
reg wr1,wr2;
always@(posedge clk_150m or negedge rst_n)
    if(!rst_n)
        begin
            wr1 <= 1'd0;
            wr2 <= 1'd0;
        end
    else 
        {wr2,wr1} <= {wr1,wr};
            

wire rd = rdn | cs0;            
wire wr = wrn | cs0;

assign db = rd ? 16'hzzzz : data_out;
assign led_red = 1'd1;
assign led_green = 1'd0;
assign led_blue = 1'd1;

endmodule

源代码下载链接：

链接：http://pan.baidu.com/s/1jHFNhwq 密码：qktz

iCore4链接：