0.ABSTRACT
（1）non-volatile memory——low standby power
DRAM——high performance and better active power
（2）we：
present a runtime-adaptive method of DRAM decay——reduce DRAM refresh energy （large
standby power due to refresh）
present two methods——DRAM bypass and dirty data keeping—— reduction in refresh energy and memory access latency
1.Introduction
(1) In the hybrid main memory:
DRAM works as—— a cache（ lower latency and smaller power consumption in
read and write than PRAM）
PRAM works as——a large background main memory（low standby power ）
(2)if a memory access request to DRAM gives a miss, the data are fetched
from PRAM to DRAM and sent to the core which issued the request.
(3)in order to reduce DRAM refresh energy, in our work, data in DRAM decay over time（popular method）
2.Related Work
（1）Existing
one to exploit low power modes——maximally utilize low power modes；
the other to minimize refresh power—— (1) minimizing the number of rows to be refreshed while having the typical refresh period of 64ms, (2) maximizing refresh period (e.g., a refresh period of 128ms or 256ms)
3.Preliminaries
?
Note that a newly allocated DRAM row (the one which receives valid data from PRAM) can serve requests for 64ms without refresh.It is because data copy from PRAM to DRAM performs ACT and PRE commands to the row. Thus, the contents in the row can remain valid for 64ms without any additional DRAM refresh.
4.Basic Idea
We present three ideas for the power management of hybrid DRAM/PRAM main memory.
-
Runtime-adaptive time out control to minimize the total energy of DRAM and PRAM while meeting the given
performance constraint set by the designer（we propose a sampling-based method of dynamic TO adjustment.）
-
Bypassing DRAM to exploit the cases of reading data with low spatial locality
-
Applying a long time out to dirty data to exploit write coalescing thereby reducing PRAM writes（we propose keeping dirty data in DRAM for a longer period than clean data）
5.Proposed Power Management
?
5.1 V,C,D
6.Experiments
7.Conclusion