One of the key differences between the PCI Express bus and the older PCI is the bus topology.
PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data and control lines. In contrast, PCI Express is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). Due to its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction.
Point-to-point architecture
At 2.5Gsps, the PCI Express Gen1 line speed is a whopping 75 times faster than the 33MHz legacy PCI speed.
How is that possible? only because PCI express is a point-to-point bus.
Remember how PCI is a shared bus?
With PCI, ample time has to be specified to let the signals settle during each clock cycle. That's because each line of the PCI bus is shared along the PCI connectors and boards on the same bus. With PCI Express, each signal is point-to-point, which means there is no more settling time and the line speeds can be much higher.
So for example, if a motherboard has two 1-lane connectors and one 16-lane connector, that requires 6+6+34=46 pins on the bridge just for the REFCLKs, PERs and PETs (since no sharing is allowed).