交通灯控制器的verilog实现

用状态机实现交通灯控制器，仿真通过，有代码以及testbench。

---

要求：

方向1是主干道，绿灯时间较长，交通灯状态循环为：

绿：40

黄：5

左：15

黄：5

红：55

方向2不是主干道，绿灯时间较少，交通灯状态循环为：

红：65

绿：30

黄：5

左：15

黄：5

---

 注意：

1. 此处将两个交通灯的状态合在一起，从而便于对两个等进行同步控制。将两个灯的5个状态合为8个状态，即：

绿1：40

黄1：5

左1：15

黄1：5

绿2：30

黄2：5

左2：15

黄2：5

对状态转换以及输出控制采用组合逻辑，在调试的过程中也曾使用时序逻辑来实现，仿真发现各种时序混乱。

在状态转换控制中，在change有效后，马上将其清零，代码如下，这是为了便于控制，调试时，发现这样比较方便，其他方法易出错。

在仿真图上就看不到change有效过，但仿真图上的其他信号是正确的。

    G2   : if(trigger)  
                           nxt_state = G1;
           else if(change)  
                  begin
                        change = 1'b0;
                        nxt_state = Y2_1;

---

代码如下：

module traffic_light(rst_n,
                            clk,
                            trigger, //触发信号，使得状态机进入循环
                            light1,
                            light2
                                 );
input rst_n;
input clk;
input trigger;

output [3:0] light1;   //4bit分别对应绿、黄、左、红灯
output [3:0] light2;

//灯亮时间
parameter G1_T = 7'd40;  //方向1的亮灯时间
parameter Y1_T = 7'd5;
parameter L1_T = 7'd15;

parameter G2_T = 7'd30;    //方向2的亮灯时间
parameter Y2_T = 7'd5;
parameter L2_T = 7'd15;

//状态编码
parameter IDLE = 4'd0;    //此处为了方便采用简单的binary编码，可用one-hot或gray提高性能
parameter G1 = 4'd1;
parameter Y1_1 = 4'd2;
parameter L1 = 4'd3;
parameter Y1_2 = 4'd4;

parameter G2 = 4'd5;
parameter Y2_1 = 4'd6;
parameter L2 = 4'd7;
parameter Y2_2 = 4'd8;

reg [3:0] cur_state;
reg [3:0] nxt_state;

reg [3:0] light1;
reg [3:0] light2;

reg [3:0] light1_tmp;
reg [3:0] light2_tmp;

reg [6:0] light_t_tmp;
reg [6:0] light_t;

reg change;
reg start;

//状态寄存，时序逻辑
always@(posedge clk)
    if(!rst_n)
        cur_state <= IDLE;
    else
        cur_state <= nxt_state;

//状态转换，组合逻辑        
always@(*)
    if(!rst_n)
        begin
            //start <= 1'b0;
            nxt_state = IDLE;
        end
    else  
        begin
            case(cur_state)
                IDLE : //if(change) 
                        if(trigger)  //状态机通过trigger进入状态循环
                            begin
                                //start <= 1'b1;  //start与计数值light_t_tmp是同步的，因此一同写在输出控制中 
                                nxt_state = G1;  //状态变换由组合逻辑实现，采用阻塞赋值即=，而非<=
                            end
                G1   : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                                begin
                                    //start <= 1'b1;
                                    change = 1'b0;
                                    nxt_state = Y1_1;
                                end
                Y1_1 : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = L1;
                            end
                L1   : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = Y1_2;
                            end
                Y1_2 : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = G2;
                            end
                G2   : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = Y2_1;
                            end
                Y2_1 : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state= L2;
                            end
                L2   : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = Y2_2;
                            end
                Y2_2 : if(trigger)  
                            begin
                                //start <= 1'b1;
                                nxt_state = G1;
                            end
                        else if(change)  
                            begin
                                //start <= 1'b1;
                                change = 1'b0;
                                nxt_state = G1;
                            end
                default : nxt_state = IDLE;
            endcase
        end        
        
//输出控制，组合逻辑
//start与计数值light_t_tmp是同步的，因此一同写在输出控制中 
//always@(posedge clk)   //输出为组合逻辑，因此不在clk下动作
always@(*)
    if(!rst_n)
        begin
            start = 1'b0;
            light_t_tmp = 7'd0;
            light1_tmp = 4'b0000;
            light2_tmp = 4'b0000;
        end
    else case(cur_state)
            G1   : begin
                        start = 1'b1;
                        light_t_tmp = G1_T;
                        light1_tmp = 4'b1000;
                        light2_tmp = 4'b0001;                    
                     end
            Y1_1 : begin
                        start = 1'b1;
                        light_t_tmp = Y1_T;
                        light1_tmp = 4'b0100;
                        light2_tmp = 4'b0001;                
                     end
            L1   : begin
                        start = 1'b1;
                        light_t_tmp = L1_T;
                        light1_tmp = 4'b0010;
                        light2_tmp = 4'b0001;                
                     end
            Y1_2 : begin
                        start = 1'b1;
                        light_t_tmp = Y1_T;
                        light1_tmp = 4'b0100;
                        light2_tmp = 4'b0001;                
                     end
            G2   : begin
                        start = 1'b1;
                        light_t_tmp = G2_T;
                        light1_tmp = 4'b0001;
                        light2_tmp = 4'b1000;                
                     end
            Y2_1 : begin
                        start = 1'b1;
                        light_t_tmp = Y2_T;
                        light1_tmp = 4'b0001;
                        light2_tmp = 4'b0100;                
                     end
            L2   : begin
                        start = 1'b1;
                        light_t_tmp = L2_T;
                        light1_tmp = 4'b0001;
                        light2_tmp = 4'b0010;                
                     end
            Y2_2 : begin
                        start = 1'b1;
                        light_t_tmp = Y2_T;
                        light1_tmp = 4'b0001;
                        light2_tmp = 4'b0100;                
                     end
        endcase

//灯亮时间倒计时
//时序逻辑，要在clk时钟下动作
always@(posedge clk)
    if(!rst_n)
        begin
            light_t <= 7'd0;
        end
    else if(start)
                begin
                    start <= 1'b0;
                    light_t <= light_t_tmp;
                end
         else
            begin
                light_t <= light_t - 1'b1;
            end
            
//在light_t减到2时，置为change信号
//用组合逻辑
always@(*)
    if(!rst_n)
        change = 1'b0;  
    else if(light_t == 4'd2)
        change = 1'b1;
        
//输出寄存    
always@(posedge clk)
    if(!rst_n)
        begin
            light1 <= 4'd0;
            light2 <= 4'd0;
        end
    else
        begin
            light1 <= light1_tmp;
            light2 <= light2_tmp;
        end
        
//下面是调试过程中对change以及start的控制    
//因为使用了时序逻辑，导致各种错误
/*
always@(posedge clk)
    if(!rst_n)
        begin
            light_t <= 7'd0;
            //change <= 1'b0;  //复位，开始状态转换
        end
    else if(start)
                begin
                    start <= 1'b0;
                    //change <= 1'b0;
                    //change_r <= 1'b0;
                    light_t <= light_t_tmp;
                end
            //else if(light_t == 4'd1)
            //        change <= 1'b1;
                 else
                    begin
                        light_t <= light_t - 1'b1;
                        //change <= 1'b0;
                    end
*/
            
/*            
always@(*)
    if(!rst_n)
        change = 1'b0;  //复位，开始状态转换
    else if(start)
            change = 1'b0;
        else if(light_t == 4'd1)
        else if(light_t == 4'd2)
            change = 1'b1;        
*/    

endmodule

testbench如下：

module traffic_light_tb;

    // Inputs
    reg rst_n;
    reg clk;
    reg trigger;

    // Outputs
    wire [3:0] light1;
    wire [3:0] light2;

    // Instantiate the Unit Under Test (UUT)
    traffic_light uut (
        .rst_n(rst_n), 
        .clk(clk), 
        .trigger(trigger),
        .light1(light1), 
        .light2(light2)
    );
    
    parameter CLK_PERIOD = 10;

    initial begin
        rst_n = 0;
        clk = 1;
        trigger = 0;

        #100;    
        rst_n = 1;
        trigger = 1;   //初始给出trigger信号，使得状态机进行状态循环
        #CLK_PERIOD trigger = 0;
        
        //#1000 trigger = 1;  //trigger复位状态机
        //#100 trigger = 0;
        
    end
    
    always #(CLK_PERIOD/2) clk = ~clk;
      
endmodule

ISIM仿真结果：

可以看到，两个交通灯从给定的状态间循环，且时间同步。