自动售饮料机的verilog实现

自动售饮料机的verilog实现。

每瓶饮料2.5元，可投入0.5与1.0两种硬币，具有找零功能。

说明：此处只是功能的简单实现，没有过多考虑实际售饮料机功能的完整性，可根据需要在此基础上进行修改，、。

代码：

module drink_seller(rst_n,
                            clk,
                            buy,
                            money,
                            drink,
                            change
                                 );
input rst_n;
input clk;
input buy;
input [1:0] money;

output drink;
output [1:0] change;

parameter IDLE = 6'b000001;  //空闲状态
parameter S0 = 6'b000010;     //投币0.5元
parameter S1 = 6'b000100;     //投币0.5元
parameter S2 = 6'b001000;    //投币1.0元
parameter S3 = 6'b010000;    //投币1.5元
parameter S4 = 6'b100000;    //投币2.0元

reg [5:0] cur_state;
reg [5:0] nxt_state;

reg drink;
reg [1:0] change;

//状态寄存，时序逻辑
always@(posedge clk)
    if(!rst_n)
        cur_state <= 6'b0;
    else
        cur_state <= nxt_state;

//状态转换，组合逻辑        
always@(*)
    if(!rst_n)
        //nxt_state = 6'b0;
        nxt_state = IDLE;
    else
        begin
            case(cur_state)
            IDLE : if(buy)
                        nxt_state = S0;
                     else
                       nxt_state = IDLE;
            S0 : case(money)   //开始投币
                         2'b00 :    nxt_state = S0;
                         2'b01 :    nxt_state = S1;
                         2'b10 :    nxt_state = S2;
                         2'b11 :    nxt_state = S3;         
                     endcase
            S1 : case(money)   //已投币0.5
                         2'b00 :    nxt_state = S1;
                         2'b01 :    nxt_state = S2;
                         2'b10 :    nxt_state = S3;
                         2'b11 :    nxt_state = S4;         
                     endcase    
            S2 : case(money)    //已投币1.0
                         2'b00 :    nxt_state = S2;
                         2'b01 :    nxt_state = S3;
                         2'b10 :    nxt_state = S4;
                         2'b11 :    nxt_state = IDLE;         
                     endcase
            S3 : case(money)    //已投币1.5
                         2'b00 :    nxt_state = S3;
                         2'b01 :    nxt_state = S4;
                         2'b10 :    nxt_state = IDLE;
                         2'b11 :    nxt_state = IDLE;         
                     endcase
            S4 : case(money)    //已投币2.0
                         2'b00 :    nxt_state = S4;
                         2'b01 :    nxt_state = IDLE;
                         2'b10 :    nxt_state = IDLE;
                         2'b11 :    nxt_state = IDLE;
                     endcase
            endcase
        end
        
//输出控制，组合逻辑        
always@(*)
    if(!rst_n)
        begin
            drink = 1'b0;
            change = 2'b00;
        end
    else begin
            case(cur_state)
            IDLE,S0,S1: 
                        begin 
                            drink = 1'b0;
                            change = 2'b00;
                        end
            S2 : case(money)
                        2'b11 :    
                             begin 
                                drink = 1'b1;
                                change = 2'b00;
                            end
                         default : 
                            begin 
                                drink = 1'b0;
                                change = 2'b00;
                            end
                     endcase
            S3 : case(money)
                         2'b10 :    
                            begin 
                                drink = 1'b1;
                                change = 2'b00;
                            end
                         2'b11 :    
                            begin 
                                drink = 1'b1;
                                change = 2'b01;
                            end
                        default : 
                            begin 
                                drink = 1'b0;
                                change = 2'b00;
                            end                     
                     endcase
            S4 : case(money)
                         2'b01 :    
                            begin 
                                drink = 1'b1;
                                change = 2'b00;
                            end
                         2'b10 :    
                            begin 
                                drink = 1'b1;
                                change = 2'b01;
                            end
                         2'b11 :    
                            begin 
                                drink = 1'b1;
                                change = 2'b11;
                            end
                        default : 
                            begin 
                                drink = 1'b0;
                                change = 2'b00;
                            end                     
                     endcase
            endcase
        end

endmodule

testbench：

module drink_seller_tb;

    // Inputs
    reg rst_n;
    reg clk;
    reg buy;
    reg [1:0] money;

    // Outputs
    wire drink;
    wire [1:0] change;

    // Instantiate the Unit Under Test (UUT)
    drink_seller uut (
        .rst_n(rst_n), 
        .clk(clk), 
        .buy(buy),
        .money(money), 
        .drink(drink), 
        .change(change)
    );
    
    parameter CLK_PERIOD = 10;

    initial begin
        rst_n = 0;
        clk = 1;
        buy = 0;
        money = 0;

        #100;
        rst_n = 1;
        # CLK_PERIOD buy = 1;
        # CLK_PERIOD buy = 0;
        
        # 100 buy = 1;
        # CLK_PERIOD buy = 0;
        
        # 100 buy = 1;        
    
    end    
        
    always #(CLK_PERIOD/2) clk = ~clk;
    
    always@(posedge clk)
    if(!rst_n)
      money = 2'b00;
     else
      money = 2'b01;

endmodule

ISIM仿真结果：