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Processor technologies
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Processor technologies
Models
Turing machine
Universal
Post–Turing
Quantum
Belt machine
Stack machine
Finite-state machine
with datapath
Hierarchical
Queue automaton
Register machines
Counter
Pointer
Random-access
Random-access stored program
Architecture
Microarchitecture
Von Neumann
Harvard
modified
Dataflow
Transport-triggered
Cellular
Endianness
Memory access
NUMA
HUMA
Load/store
Register/memory
Cache hierarchy
Memory hierarchy
Virtual memory
Secondary storage
Heterogeneous
Fabric
Multiprocessing
Cognitive
Neuromorphic
Instruction set
architectures
Types
CISC
RISC
Application-specific
EDGE
TRIPS
VLIW
EPIC
MISC
OISC
NISC
ZISC
Comparison
Addressing modes
Instruction sets
x86
ARM
MIPS
Power ISA
SPARC
Itanium
Unicore
MicroBlaze
RISC-V
LMC
Others
Execution
Instruction pipelining
Pipeline stall
Operand forwarding
Classic RISC pipeline
Hazards
Data dependency
Structural
Control
False sharing
Out-of-order
Tomasulo algorithm
Reservation station
Re-order buffer
Register renaming
Speculative
Branch prediction
Memory dependence prediction
Parallelism
Level
Bit
Bit-serial
Word
Instruction
Pipelining
Scalar
Superscalar
Task
Thread
Process
Data
Vector
Memory
Distributed
Multithreading
Temporal
Simultaneous
Hyperthreading
Speculative
Preemptive
Cooperative
Flynn's taxonomy
SISD
SIMD
SWAR
SIMT
MISD
MIMD
SPMD
Processor
performance
Transistor count
Instructions per cycle
(IPC)
Cycles per instruction
(CPI)
Instructions per second
(IPS)
Floating-point operations per second
(FLOPS)
Transactions per second
(TPS)
Synaptic updates per second
(SUPS)
Performance per watt
(PPW)
Cache performance metrics
Computer performance by orders of magnitude
Types
Central processing unit
(CPU)
Graphics processing unit
(GPU)
GPGPU
Vector
Barrel
Stream
Coprocessor
ASIC
FPGA
CPLD
Multi-chip module
(MCM)
System in package
(SiP)
By application
Microprocessor
Microcontroller
Mobile
Notebook
Ultra-low-voltage
ASIP
Systems
on chip
System on a chip
(SoC)
Multiprocessor
(MPSoC)
Programmable
(PSoC)
Network on a chip
(NoC)
Hardware
accelerators
AI accelerator
Vision processing unit
(VPU)
Physics processing unit
(PPU)
Digital signal processor
(DSP)
Tensor processing unit
(TPU)
Secure cryptoprocessor
Network processor
Baseband processor
Word size
1-bit
4-bit
8-bit
12-bit
15-bit
16-bit
32-bit
48-bit
64-bit
128-bit
256-bit
512-bit
bit slicing
others
variable
Core count
Single-core
Multi-core
Manycore
Heterogeneous architecture
Components
Core
Cache
CPU cache
replacement policies
coherence
Bus
Clock rate
Clock signal
FIFO
Functional units
Arithmetic logic unit
(ALU)
Address generation unit
(AGU)
Floating-point unit
(FPU)
Memory management unit
(MMU)
Load–store unit
Translation lookaside buffer
(TLB)
Integrated memory controller
(IMC)
Logic
Combinational
Sequential
Glue
Logic gate
Quantum
Array
Registers
Processor register
Status register
Stack register
Register file
Memory buffer
Program counter
Control unit
Instruction unit
Data buffer
Write buffer
Microcode
ROM
Counter
Datapath
Multiplexer
Demultiplexer
Adder
Multiplier
CPU
Binary decoder
Address decoder
Sum addressed decoder
Barrel shifter
Circuitry
Integrated circuit
3D
Mixed-signal
Power management
Boolean
Digital
Analog
Quantum
Switch
Power
management
PMU
APM
ACPI
Dynamic frequency scaling
Dynamic voltage scaling
Clock gating
Performance per watt
(PPW)
Race to sleep
Related
History of general-purpose CPUs
Microprocessor chronology
Processor design
Digital electronics
Hardware security module
Semiconductor device fabrication
Tick–tock model
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原文地址:https://www.cnblogs.com/Kimbing-Ng/p/12830213.html
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