这次调试用了很长时间，问题主要出在按键上，经过这次调试总结的经验
1注意警告有时候警告也有用；
2学会了建立tcl文档
3如果实在找不出错误的话，可以重新写一遍，一个模块一个模块的实现，这样效率比较高
4.按键检测模块写的太麻烦了，以后需要优化
module top
(
CLK,RSTn,SMG1,SMG2,SMG3,SMG4,SMG5,SMG6,Pin_In1,Pin_In2,Pin_In3
);
input CLK;
input RSTn;
input Pin_In1;
input Pin_In2;
input Pin_In3;
output [7:0]SMG1;
output [7:0]SMG2;
output [7:0]SMG3;
output [7:0]SMG4;
output [7:0]SMG5;
output [7:0]SMG6;
/****************************/
wire [2:0]HL_Sig;
wire [2:0]LH_Sig;
button_jiance U1
(
.CLK(CLK),
.RSTn(RSTn),
.Pin_In2(Pin_In2),
.Pin_In1(Pin_In1),
.Pin_In3(Pin_In3),
.HL_Sig(HL_Sig),
.LH_Sig(LH_Sig)
);
display U2
(
.CLK(CLK),
.RSTn(RSTn),
.HL_Sig(HL_Sig),
.LH_Sig(LH_Sig),
.SMG1(SMG1),
.SMG2(SMG2),
.SMG3(SMG3),
.SMG4(SMG4),
.SMG5(SMG5),
.SMG6(SMG6),
);
endmodule
module button_jiance
(
CLK,RSTn,Pin_In1,Pin_In2,HL_Sig,LH_Sig,Pin_In3
);
input CLK;
input RSTn;
input Pin_In1;//按键输入
input Pin_In2;
input Pin_In3;
output [2:0]HL_Sig;//高到低电平变化
output [2:0]LH_Sig;//低到高电平变化
reg HL_Sig1;
reg HL_Sig2;
reg LH_Sig1;
reg LH_Sig2;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
HL_Sig1<=1'b1;
HL_Sig2<=1'b1;
LH_Sig1<=1'b0;
LH_Sig1<=1'b0;
end
else
begin
HL_Sig1<=Pin_In2;
HL_Sig2<=HL_Sig1;
LH_Sig1<=Pin_In2;
LH_Sig2<=LH_Sig1;
end
/*****************************/
reg HL_Sig3;
reg HL_Sig4;
reg LH_Sig3;
reg LH_Sig4;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
HL_Sig3<=1'b1;
HL_Sig4<=1'b1;
LH_Sig3<=1'b0;
LH_Sig4<=1'b0;
end
else
begin
HL_Sig3<=Pin_In3;
HL_Sig4<=HL_Sig3;
LH_Sig3<=Pin_In3;
LH_Sig4<=LH_Sig3;
end
reg [1:0]Sig1;
reg [1:0]Sig;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
Sig<=2'b00;
Sig1<=2'b00;
end
else
begin
Sig1[0]<=Pin_In1;
Sig[0]<=Sig1[0];
end
assign HL_Sig[0]=!Sig1[0]&Sig[0];
assign LH_Sig[0]=Sig1[0]&!Sig[0];
assign HL_Sig[1]=!HL_Sig1&HL_Sig2;
assign LH_Sig[1]=!LH_Sig2&LH_Sig1;
assign HL_Sig[2]=!HL_Sig3&HL_Sig4;
assign LH_Sig[2]=!LH_Sig4&LH_Sig3;
endmodule
module display
(
CLK,RSTn,HL_Sig,LH_Sig,SMG1,SMG2,SMG3,SMG4,SMG5,SMG6
);
input CLK;
input RSTn;
input [2:0]HL_Sig;
input [2:0]LH_Sig;
output[7:0]SMG1;
output[7:0]SMG2;
output[7:0]SMG3;
output[7:0]SMG4;
output[7:0]SMG5;
output[7:0]SMG6;
/*******************************/
/*---------dingshiqi-----------*/
reg [19:0]Count;
parameter TIME_10MS=499_999;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
Count<=20'd0;
else if(Count==TIME_10MS)
Count<=20'd0;
else if((!isCount)&&(!isCount1)&&(!isCount2))
Count<=20'd0;
else if(isCount||isCount1||isCount2)
Count<=Count+1'b1;
/**************************/
/*-----anjianxiaodou--*/
reg rPin;//anjianshuchu
reg rPin1;
reg rPin2;
reg[1:0]i;
reg[1:0]i1;
reg[1:0]i2;
reg isCount;
reg isCount1;
//anjain1
reg isCount2;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
i<=2'b0;
rPin<=1'b0;
end
else
case(i)
2'd0:
if(HL_Sig[0])
i<=2'd1;
else if(LH_Sig[0])
i<=2'd3;
2'd1:
if(Count==TIME_10MS)
begin
i<=2'd2;
isCount<=1'd0;
rPin<=1'd1;
end
else
isCount<=1'b1;
2'd2:
begin
i<=2'd0;
rPin<=1'd0;
end
2'd3:
if(Count==TIME_10MS)
begin
i<=2'd0;
isCount<=1'd0;
end
else
isCount<=1'b1;
endcase
/*************************/
/**--anjain2------*/
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
i1<=2'b0;
rPin1<=1'b0;
end
else
case(i1)
2'd0:
if(HL_Sig[1])
i1<=2'd1;
else if(LH_Sig[1])
i1<=2'd3;
2'd1:
if(Count==TIME_10MS)
begin
i1<=2'd2;
isCount1<=1'd0;
rPin1<=1'd1;
end
else
isCount1<=1'b1;
2'd2:
begin
i1<=2'd0;
rPin1<=1'd0;
end
2'd3:
if(Count==TIME_10MS)
begin
i1<=2'd0;
isCount1<=1'd0;
end
else
isCount1<=1'b1;
endcase
/**--anjain3------*/
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
i2<=2'b0;
rPin2<=1'b0;
end
else
case(i2)
2'd0:
if(HL_Sig[2])
i2<=2'd1;
else if(LH_Sig[2])
i2<=2'd3;
2'd1:
if(Count==TIME_10MS)
begin
i2<=2'd2;
isCount2<=1'd0;
rPin2<=1'd1;
end
else
isCount2<=1'b1;
2'd2:
begin
i2<=2'd0;
rPin2<=1'd0;
end
2'd3:
if(Count==TIME_10MS)
begin
i2<=2'd0;
isCount2<=1'd0;
end
else
isCount2<=1'b1;
endcase
/*---先定义一个1S的计数器 jiajian-*/
parameter TIME_1S=28'd49_999_999;//1s时间
//0~9的键值
parameter _0=8'hc0,_1=8'hf9,_2=8'ha4,_3=8'hb0,_4=8'h99,
_5=8'h92,_6=8'h82,_7=8'hf8,_8=8'h80,_9=8'h90;
/*****************************/
/*********************************/
reg[27:0]Count1;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
Count1<=28'd0;
else if(Count1==TIME_1S)
Count1<=28'd0;
else if(!key)
Count1<=Count1+1'b1;
/**************************/
/*************************/
/******************************/
//按键
always@(posedge CLK or negedge RSTn)
if(!RSTn)
key<=3'd0; //key等于0的时候开始计时
else
begin
if(key==4)
key<=3'd0;
else if(rPin)
key<=key+1'b1;
end
/*---计数时间秒--*/
reg[7:0]TIME_S;
reg[7:0]TIME_F;
reg[7:0]TIME_H;
reg[2:0]key;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
TIME_S<=8'd0;
TIME_F<=8'd0;
TIME_H<=8'd0;
end
else if(TIME_S==8'd60)
begin
TIME_S<=8'd0;
TIME_F<=TIME_F+1'b1;
end
else if(Count1==TIME_1S)
TIME_S<=TIME_S+1'b1;
else if(TIME_F==8'd60)
begin
TIME_F<=8'd0;
TIME_H<=TIME_H+1'b1;
end
else if(TIME_H==8'd24)
TIME_H<=8'd0;
else
case(key)
3'd1:begin
if(rPin1)
begin
if(TIME_S==60)
TIME_S<=8'd0;
else TIME_S<=TIME_S+1'b1;
end
else if(rPin2)
begin
if(TIME_S==8'd0)
TIME_S<=8'd59;
else TIME_S<=TIME_S-1'b1;
end
end
3'd2:begin
if(rPin1)
begin
if(TIME_F==60)
TIME_F<=8'd0;
else TIME_F<=TIME_F+1'b1;
end
else if(rPin2)
begin
if(TIME_F==8'd0)
TIME_F<=8'd59;
else TIME_F<=TIME_F-1'b1;
end
end
3'd3:begin
if(rPin1)
begin
if(TIME_H==24)
TIME_H<=8'd0;
else TIME_H<=TIME_H+1'b1;
end
else if(rPin2)
begin
if(TIME_H==8'd0)
TIME_H<=8'd23;
else TIME_H<=TIME_H-1'b1;
end
end
endcase
/*else if(rPin)
begin
TIME_F<=TIME_F+1'b1;
end
else if(rPin1)
begin
TIME_H<=TIME_H+1'b1;
end
else if(rPin2)
TIME_F<=TIME_F+1'b1;*/
reg[7:0] rSMG1;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG1[7:0]<=8'hff;
else
case(TIME_S%10)
4'd0:rSMG1<=_0;
4'd1:rSMG1<=_1;
4'd2:rSMG1<=_2;
4'd3:rSMG1<=_3;
4'd4:rSMG1<=_4;
4'd5:rSMG1<=_5;
4'd6:rSMG1<=_6;
4'd7:rSMG1<=_7;
4'd8:rSMG1<=_8;
4'd9:rSMG1<=_9;
default:rSMG1<=8'hff;
endcase
reg[7:0] rSMG2;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG2[7:0]<=8'hff;
else
case(TIME_S/10)
4'd0:rSMG2<=_0;
4'd1:rSMG2<=_1;
4'd2:rSMG2<=_2;
4'd3:rSMG2<=_3;
4'd4:rSMG2<=_4;
4'd5:rSMG2<=_5;
4'd6:rSMG2<=_6;
4'd7:rSMG2<=_7;
4'd8:rSMG2<=_8;
4'd9:rSMG2<=_9;
default:rSMG2<=8'hff;
endcase
/********************************/
/********************/
/*-显示时间f--*/
reg[7:0] rSMG3;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG3[7:0]<=8'hff;
else
case(TIME_F%10)
4'd0:rSMG3<=_0;
4'd1:rSMG3<=_1;
4'd2:rSMG3<=_2;
4'd3:rSMG3<=_3;
4'd4:rSMG3<=_4;
4'd5:rSMG3<=_5;
4'd6:rSMG3<=_6;
4'd7:rSMG3<=_7;
4'd8:rSMG3<=_8;
4'd9:rSMG3<=_9;
default:rSMG3<=8'hff;
endcase
reg[7:0] rSMG4;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG4[7:0]<=8'hff;
else
case(TIME_F/10)
4'd0:rSMG4<=_0;
4'd1:rSMG4<=_1;
4'd2:rSMG4<=_2;
4'd3:rSMG4<=_3;
4'd4:rSMG4<=_4;
4'd5:rSMG4<=_5;
4'd6:rSMG4<=_6;
4'd7:rSMG4<=_7;
4'd8:rSMG4<=_8;
4'd9:rSMG4 <=_9;
default:rSMG4<=8'hff;
endcase
/********************************/
/********************/
/*-显示时间H--*/
reg[7:0] rSMG5;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG5[7:0]<=8'hff;
else
case(TIME_H%10)
4'd0:rSMG5<=_0;
4'd1:rSMG5<=_1;
4'd2:rSMG5<=_2;
4'd3:rSMG5<=_3;
4'd4:rSMG5<=_4;
4'd5:rSMG5<=_5;
4'd6:rSMG5<=_6;
4'd7:rSMG5<=_7;
4'd8:rSMG5<=_8;
4'd9:rSMG5<=_9;
default:rSMG5<=8'hff;
endcase
reg[7:0] rSMG6;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
rSMG6[7:0]<=8'hff;
else
case(TIME_H/10)
4'd0:rSMG6<=_0;
4'd1:rSMG6<=_1;
4'd2:rSMG6<=_2;
4'd3:rSMG6<=_3;
4'd4:rSMG6<=_4;
4'd5:rSMG6<=_5;
4'd6:rSMG6<=_6;
4'd7:rSMG6<=_7;
4'd8:rSMG6<=_8;
4'd9:rSMG6<=_9;
default:rSMG6<=8'hff;
endcase
/**********************************/
assign SMG1=rSMG1;
assign SMG2=rSMG2;
assign SMG3=rSMG3;
assign SMG4=rSMG4;
assign SMG5=rSMG5;
assign SMG6=rSMG6;
endmodule