SystemVerilog 序列运算符与属性运算符

1. 需要注意的是 nonconsecutive [=M:N]和 goto repetition[-> M:N]的区别 

例子(SVA handbook)

a ##1 b[=2] ##1 c //a x x b x x x b x x c , then anytime later, c is ture

a ##1 b[->2] ##1 c //a x x b x x x b c, at next cycle, c is ture

consecutive range的例子

a ##1 b[*1:5] ##1 c //a b b b b c 与上面的区别在于，所有的信号关系都是时钟连续的 

2. Property operator 中|-> 与|=>，前者是要求在同一仿真时间标记上，a |-> b，对a和b做判断；而如果替换为后者，则只需要在下一个时钟周期（clock tick），进行判断。简单的记法就是"="视为是两个手指，non-overlap, “-”则可以形象地视为是overlap.

3. assert, assume, cover, expect四者之间的区别。

 assert
used to enforce a property as a check

 assume
used to allow properties to be considered as assumptions or constraints for formal analysis. 与assert不同，assume并不支持action block

 cover
used to collect information about the evaluation and report the results at the end the simulation. 同样的方式也可以在assert的action block中，通过调用自定义的task来更新statistics.

 cover一般所包含的结果，# of times attempted, # of times succeeded, # of times failed, # of times succeeded because of vacuity，四个部分

 expect(p177)
not part of "verification layer" because it does not make a statement about what should be done with a property in terms of verification.也就是说与verification任务无关。但是它可以改变程序的控制流，根据相应的property满足或不满足，执行相应的action block。感觉和assert差不多。

附注 

Sequence operators

Operator Comments 

##M or 

##[M:N]   Concatenation, a ##[1:4] b，a/b两个信号之间1-4个时钟周期

[*M] or 

[*M:N]  repetition, s[*1:3]重复一到三次，也可以用## + or 得到等效的，注意这是consecutive的与[=1:3]有区别

[-> M] or [-> M:N] goto repetition

Verfication Directives

Cocurrent assertion:

assert property(property_spec) action_bllock

action_block ::= assertion_or_null

| [statement] else statement_or_null 

immediate assertion

assert (expression) action block 

assume property(property_spec);

cover property (property_spec) statement_or_null;

expect (property_spec) action_block 

Reference

VMM for SystemVerilog 

SystemVerilog Assertions Handbook