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  • FPGA之verilog静态数码管小程序

    话不多说直接上代码:

    module shumaguan0_9(
    clk,
    rst_n,
    conlig,    //位选信号
    dataout   //数码管控制信号,由低到高依次为dp,a,b,c,d,e,f,g
    );

    input clk;
    input rst_n;
    output[3:0] conlig;
    output[7:0] dataout;

    reg[3:0] conlig;
    reg[7:0] dataout;
    reg[25:0] cnt;

    always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
    cnt <= 0;
    end
    else if(cnt == 49_999_999)begin
    cnt <= 0;
    end
    else begin
    cnt <= cnt+1;
    end
    end

    always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
    conlig <= 4'b1110;
    end
    else begin
    conlig <= conlig;
    end
    end

    always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
    dataout <= 8'b1000_0000;
    end
    else if(cnt == 49_999_999)begin
    if(dataout == 8'b1000_0000)begin
    dataout <= 8'b1111_0011;
    end
    else if(dataout == 8'b1111_0011)begin
    dataout <= 8'b0100_1001;
    end
    else if(dataout == 8'b0100_1001)begin
    dataout <= 8'b0110_0001;
    end
    else if(dataout == 8'b0110_0001)begin
    dataout <= 8'b0011_0011;
    end
    else if(dataout == 8'b0011_0011)begin
    dataout <= 8'b0010_0101;
    end
    else if(dataout == 8'b0010_0101)begin
    dataout <= 8'b0000_0101;
    end
    else if(dataout == 8'b0000_0101)begin
    dataout <= 8'b1111_0001;
    end
    else if(dataout == 8'b1111_0001)begin
    dataout <= 8'b0000_0001;
    end
    else if(dataout == 8'b0000_0001)begin
    dataout <= 8'b0010_0001;
    end
    else if(dataout == 8'b0010_0001)begin
    dataout <= 8'b1000_0000;
    end
    else begin
    dataout <= dataout;
    end
    end
    end
    endmodule

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  • 原文地址:https://www.cnblogs.com/curatan/p/7419191.html
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