ixgbe dma 控制器

发送

/* Transmit DMA registers */
#define IXGBE_TDBAL(_i)        (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
#define IXGBE_TDBAH(_i)        (0x06004 + ((_i) * 0x40))
#define IXGBE_TDLEN(_i)        (0x06008 + ((_i) * 0x40))
#define IXGBE_TDH(_i)        (0x06010 + ((_i) * 0x40))
#define IXGBE_TDT(_i)        (0x06018 + ((_i) * 0x40))
#define IXGBE_TXDCTL(_i)    (0x06028 + ((_i) * 0x40))
#define IXGBE_TDWBAL(_i)    (0x06038 + ((_i) * 0x40))
#define IXGBE_TDWBAH(_i)    (0x0603C + ((_i) * 0x40))
#define IXGBE_DTXCTL        0x07E00

#define IXGBE_DMATXCTL        0x04A80
#define IXGBE_PFVFSPOOF(_i)    (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
#define IXGBE_PFDTXGSWC        0x08220
#define IXGBE_DTXMXSZRQ        0x08100
#define IXGBE_DTXTCPFLGL    0x04A88
#define IXGBE_DTXTCPFLGH    0x04A8C
#define IXGBE_LBDRPEN        0x0CA00
#define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */

#define IXGBE_DMATXCTL_TE    0x1 /* Transmit Enable */
#define IXGBE_DMATXCTL_NS    0x2 /* No Snoop LSO hdr buffer */
#define IXGBE_DMATXCTL_GDV    0x8 /* Global Double VLAN */
#define IXGBE_DMATXCTL_MDP_EN    0x20 /* Bit 5 */
#define IXGBE_DMATXCTL_MBINTEN    0x40 /* Bit 6 */
#define IXGBE_DMATXCTL_VT_SHIFT    16  /* VLAN EtherType */

接收

/* Receive DMA Registers */
#define IXGBE_RDBAL(_i)    (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : 
             (0x0D000 + (((_i) - 64) * 0x40)))
#define IXGBE_RDBAH(_i)    (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : 
             (0x0D004 + (((_i) - 64) * 0x40)))
#define IXGBE_RDLEN(_i)    (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : 
             (0x0D008 + (((_i) - 64) * 0x40)))
#define IXGBE_RDH(_i)    (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : 
             (0x0D010 + (((_i) - 64) * 0x40)))
#define IXGBE_RDT(_i)    (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : 
             (0x0D018 + (((_i) - 64) * 0x40)))
#define IXGBE_RXDCTL(_i)    (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : 
                 (0x0D028 + (((_i) - 64) * 0x40)))
#define IXGBE_RSCCTL(_i)    (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : 
                 (0x0D02C + (((_i) - 64) * 0x40)))
#define IXGBE_RSCDBU    0x03028
#define IXGBE_RDDCC    0x02F20
#define IXGBE_RXMEMWRAP    0x03190
#define IXGBE_STARCTRL    0x03024
/*

/*
 * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
 * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
 * 87500 bytes [85KB]
 */
#define IXGBE_DMACRXT_10G        0x55
#define IXGBE_DMACRXT_1G        0x09
#define IXGBE_DMACRXT_100M        0x01

/* DMA Coalescing registers */
#define IXGBE_DMCMNGTH            0x15F20 /* Management Threshold */
#define IXGBE_DMACR            0x02400 /* Control register */
#define IXGBE_DMCTH(_i)            (0x03300 + ((_i) * 4)) /* 8 of these */
#define IXGBE_DMCTLX            0x02404 /* Time to Lx request */
/* DMA Coalescing register fields */
#define IXGBE_DMCMNGTH_DMCMNGTH_MASK    0x000FFFF0 /* Mng Threshold mask */
#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT    4 /* Management Threshold shift */
#define IXGBE_DMACR_DMACWT_MASK        0x0000FFFF /* Watchdog Timer mask */
#define IXGBE_DMACR_HIGH_PRI_TC_MASK    0x00FF0000
#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT    16
#define IXGBE_DMACR_EN_MNG_IND        0x10000000 /* Enable Mng Indications */
#define IXGBE_DMACR_LX_COAL_IND        0x40000000 /* Lx Coalescing indicate */
#define IXGBE_DMACR_DMAC_EN        0x80000000 /* DMA Coalescing Enable */
#define IXGBE_DMCTH_DMACRXT_MASK    0x000001FF /* Receive Threshold mask */
#define IXGBE_DMCTLX_TTLX_MASK        0x00000FFF /* Time to Lx request mask */