有限状态机（finite state machine，FSM）

一、Moore有限状态机中，电路的输出取决于机器的状态而与其输入无关。

 1 module MooreFSM(sel, clk, z_out);
    input sel, clk;
    output z_out;
    reg z_out;
    
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
    reg [1:0] mooreState;
    
    always@(posedge clk)
        case(mooreState)
            S0:begin
                    z_out <= 1;
                    mooreState <= (!sel)?S0:S2;
                end
            S1:begin
                    z_out <= 0;
                    mooreState <= (!sel)?S0:S2;
                end
            S2:begin
                    z_out <= 0;
                    mooreState <= (!sel)?S2:S3;
                end
            S3:begin
                    z_out <= 1;
                    mooreState <= (!sel)?S1:S3;
                end
        endcase
endmodule

 二、Mealy有限状态机，输出既取决于机器状态，又取决于其输入。

module MealyFSM(sel, clk, rst, z_out);
    input sel, clk, rst;
    output z_out;
    reg z_out;
    
    parameter ST0=2'b00, ST1=2'b01, ST2=2'b10;
    reg [1:0] CurrentState, NextState;
    
    //timing logic
    always@(posedge rst or posedge clk)
        if(rst)
            CurrentState <= ST0;
        else
            CurrentState <= NextState;
            
    //combinational logic
    always@( * )
        case(CurrentState)
            ST0:begin
                z_out = sel ? 1:0;
                NextState = sel ? ST2:ST0;
            end
            ST1:begin
                z_out = sel ? 1:0;
                NextState = sel ? ST0:ST1;
            end
            ST2:begin
                z_out = 0;
                NextState = sel ? ST1:ST2;
            end
            default:begin
                z_out = 0;
                NextState = ST0;
            end
        endcase
        
endmodule