/*`timescale 1ns/100ps
`define clk_cycle 50
module testbench1;
reg clk,reset,nbusy;
reg [7:0]data;
wire ce,sck,si;
always #`clk_cycle clk=~clk;
initial
begin
reset=1;
#100 reset=0;
#100 reset=1;
#100000 $stop;
end
endmodule */
`timescale 1ns/100ps
`define clk_cycle 50
module testbench2;
reg clk,reset;
wire clk_out;
always #`clk_cycle clk=~clk;//??????
initial
begin
clk=0;
reset=1;
#10 reset=0;
#110 reset=1;
#200000 $stop;
end
// half_clk m0(.reset(reset),.clk_in(clk),.clk_out(clk_out));
endmodule
差不多的两个程序，在调试的时候上一个的clk时钟时钟为X，纠结了很久，找了很久，才发现原来clk没有给初始化，一定要仔细啊！