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Note: Do not compile any Altera model files that are located in the quartus/eda/sim_lib directory. |
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Note: VHDL logical libraries have the names listed in the table. VHDL logical libraries have a _ver suffix. |
Logical Library Name |
Library Description |
arriagx |
Arria GX |
arriagx_hssi |
Arria GX devices with transceivers |
arriaiigz |
Arria II GZ |
arriaiigz_hssi |
Arria II GZ devices with transceivers |
arriaiigz_pcie_hip |
Arria II GZ devices with PCI Express™ hard IP block |
arriaii_hssi |
Arria II GX devices with transceivers |
arriaii_pcie_hip |
Arria II devices with PCIe hard IP block |
arriaii |
Arria II GX |
cyclone |
Cyclone |
cycloneii |
Cyclone II |
cycloneiii |
Cyclone III |
cycloneiiils |
Cyclone III LS |
cycloneiv |
Cyclone IV GX devices |
cycloneive |
Cyclone IV E devices |
cycloneiv_hssi |
Cyclone IV devices with transceivers |
cycloneiv_pcie_hip |
Cyclone IV devices with PCIe hard IP block |
hardcopyii |
HardCopy II |
hardcopyiii |
HardCopy III |
hardcopyiv |
HardCopy IV |
hardcopyiv_hssi |
HardCopy IV devices with transceivers |
hardcopyiv_pcie_hip |
HardCopy IV devices with PCIe hard IP block |
max |
MAX 3000 and MAX 7000 |
maxii |
MAX II |
maxv |
MAX V |
sgate |
High-level primitives |
stratix |
Stratix |
stratixgx |
Stratix GX |
stratixgx_gxb |
Stratix GX devices with transceivers |
stratixii |
Stratix II |
stratixiigx |
Stratix II GX |
stratixiigx_hssi |
Stratix II GX devices with transceivers |
stratixiii |
Stratix III |
stratixiv |
Stratix IV |
stratixiv_hssi |
Stratix IV devices with transceivers |
stratixiv_pcie_hip |
PCIe hard IP block for Stratix IV devices |
stratixv |
Stratix V |
stratixv_hssi |
Stratix V devices with transceivers |
stratixv_pcie_hip |
PCIe hard IP block for Stratix V devices |
220model |
Altera library of parameterized modules (LPM) version 2 2 0 |
altera |
Models for Altera primitives |
altera_lnsim |
Family-independent library required for Stratix V and newer devices |
altera_mf |
Models for Altera megafunctions |