section 1

1.　　quartus setup

　　1.1　　assignment-->setting

　　1.2　　editor-> sdc file　　case sensitive

2.　　core timing

　　2.1　　create_clock

　　2.2　　derive_pll_clock

• • • create_generated_clock
    • transceiver_clock

　　2.3　　derive_clock_uncertainty

　　2.4　　set_clock_groups

• • • un-related
    • options -asynchronous,-exclusive ASIC, no matters in FPGA
    • leave out virtual clock

3.　　I/O timing

• • set_input_delay, set_output_delay
  • these constraints describe what is going on outside of the FPGA
  • virtual clock by create_clock
  • -max and -min by set_input_delay, set_output_delay
    • set_input_delay -clock virtual_clock -max/min xxx [get_ports in/out]
    • launch + delay = latch-->requirements fig
  • multicycle
    • set_multicycle_path -setup/hold -to [get_ports xxx] xxx
  • modify -max -min
    • launch + delay = latch-->requirements
    • board level clock skew = clock2destination - clock2source