3. Why Plan Partitions and Floorplan Assignments
more planning is required
setting up the design logic for partitioning
may also involve planning placement assignments to create a floorplan
more rigorous about following good design practices
3.1 Partition Boundaries and Optimization
logic optimization :
logical hierarchical boundaries between partitions are treated as hard boundaries,
Fitter can never perform logic optimizations such as physical synthesis across the partition boundary
placement optimizations :
When partitions are placed together, the Fitter can perform optimize the placement of cross-boundary paths
the Fitter does not place and route the entire cross-boundary path at the same time(ie.different projects, or previous post-fitting results) , cannot fully optimize placement across the partition boundaries.
timing performance utilization effects
these effects is possible if a flat version of your design is very close to meeting its timing requirements, or is close to using all the device resources
Partitions can increase resource utilization due to cross-boundary optimization limitations if the design does not follow partitioning guidelines.Floorplan assignments can also increase resource utilization because regions can lead to unused logic.
Partitions and floorplan assignments might increase routing utilization compared to a flat design.Review the Fitter messages to check how much time is spent during routing optimizations to determine the percentage of routing utilization.
Partitions can reduce timing performance in some cases because of the optimization and resource effects described above, causing longer logic delays.
3.1.1 Turning On Supported Cross-boundary Optimizations
improve the optimizations performed between design partitions
select the optimizations as individual assignments for each partition.
Cross-boundary optimizations are implemented top-down from the parent partition into the child partition, but not vice-versa.
Cross-boundary optimizations include the following: propagate constants, propagate inversions on partition inputs, merge inputs fed by a common source, merge electrically equivalent idirectional pins, absorb internal paths, and remove logic connected to dangling outputs.