TC297B

　　打开例程，目录树下的Includes中包含了各个片上资源对应的头文件，这些头文件定义了相应外设的寄存器地址（寄存器是内置于各个 IP 外设中，是一种用于配置外设功能的存储器，就是一种内存，并且有相对应的地址。——野火）以及操作寄存器的方法——结构体。

1.IfxPort_reg.h：定义Port寄存器地址

/** \ 定义MODULE_P13(I/O)的寄存器基地址 */
#define MODULE_P13 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B300u))

/** \ 定义MODULE_P13(I/O)的各个子寄存器地址（基地址+偏移量） */
/** addtogroup IfxLld_Port_Cfg_P13
 * {  */

/** \brief  FC, Port Access Enable Register 0 */
#define P13_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B3FCu)

/** \brief  F8, Port Access Enable Register 1 */
#define P13_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B3F8u)

/** \brief 0, Port Output Register */
#define P13_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B300u)

......

2.IfxPort_regdef.h：定义操作I/O寄存器的结构体

/** \ 定义包含所有寄存器的结构体，占用256（0x0100）个字节，即MODULE_P13的地址范围大小，见如下定义。（该方法通过定义与寄存器结构相对应的结构体，来操作寄存器） */
/* #define MODULE_P13 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B300u)) */
/* #define MODULE_P14 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B400u)) */

typedef volatile struct _Ifx_P
{
    Ifx_P_OUT OUT;                          /**< rief 0, Port Output Register */
    Ifx_P_OMR OMR;                          /**< rief 4, Port Output Modification Register */
    Ifx_P_ID ID;                            /**< rief 8, Identification Register */
    unsigned char reserved_C[4];            /**< rief C, internal Reserved */
    Ifx_P_IOCR0 IOCR0;                      /**< rief 10, Port Input/Output Control Register 0 */
    Ifx_P_IOCR4 IOCR4;                      /**< rief 14, Port Input/Output Control Register 4 */
    Ifx_P_IOCR8 IOCR8;                      /**< rief 18, Port Input/Output Control Register 8 */
    Ifx_P_IOCR12 IOCR12;                    /**< rief 1C, Port Input/Output Control Register 12 */
    unsigned char reserved_20[4];           /**< rief 20, internal Reserved */
    Ifx_P_IN IN;                            /**< rief 24, Port Input Register */
    unsigned char reserved_28[24];          /**< rief 28, internal Reserved */
    Ifx_P_PDR0 PDR0;                        /**< rief 40, Port Pad Driver Mode 0 Register */
    Ifx_P_PDR1 PDR1;                        /**< rief 44, Port Pad Driver Mode 1 Register */
    unsigned char reserved_48[8];           /**< rief 48, internal Reserved */
    Ifx_P_ESR ESR;                          /**< rief 50, Port Emergency Stop Register */
    unsigned char reserved_54[12];          /**< rief 54, internal Reserved */
    Ifx_P_PDISC PDISC;                      /**< rief 60, Port Pin Function Decision Control Register */
    Ifx_P_PCSR PCSR;                        /**< rief 64, Port Pin Controller Select Register */
    unsigned char reserved_68[8];           /**< rief 68, internal Reserved */
    Ifx_P_OMSR0 OMSR0;                      /**< rief 70, Port Output Modification Set Register 0 */
    Ifx_P_OMSR4 OMSR4;                      /**< rief 74, Port Output Modification Set Register 4 */
    Ifx_P_OMSR8 OMSR8;                      /**< rief 78, Port Output Modification Set Register 8 */
    Ifx_P_OMSR12 OMSR12;                    /**< rief 7C, Port Output Modification Set Register 8 */
    Ifx_P_OMCR0 OMCR0;                      /**< rief 80, Port Output Modification Clear Register 0 */
    Ifx_P_OMCR4 OMCR4;                      /**< rief 84, Port Output Modification Clear Register 4 */
    Ifx_P_OMCR8 OMCR8;                      /**< rief 88, Port Output Modification Clear Register 8 */
    Ifx_P_OMCR12 OMCR12;                    /**< rief 8C, Port Output Modification Clear Register 12 */
    Ifx_P_OMSR OMSR;                        /**< rief 90, Port Output Modification Set Register */
    Ifx_P_OMCR OMCR;                        /**< rief 94, Port Output Modification Clear Register */
    unsigned char reserved_98[8];           /**< rief 98, internal Reserved */
    Ifx_P_LPCR0 LPCR0;                      /**< rief A0, Port LVDS Pad Control Register 0 */
    Ifx_P_LPCR1 LPCR1;                      /**< rief A4, Port LVDS Pad Control Register 1 */
    Ifx_P_LPCR2 LPCR2;                      /**< rief A8, Port LVDS Pad Control Register 2 */
    Ifx_P_LPCR3 LPCR3;                      /**< rief AC, Port LVDS Pad Control Register 3 */
    unsigned char reserved_A4[72];          /**< rief B0, internal Reserved */
    Ifx_P_ACCEN1 ACCEN1;                    /**< rief F8, Port Access Enable Register 1 */
    Ifx_P_ACCEN0 ACCEN0;                    /**< rief FC, Port Access Enable Register 0 */
} Ifx_P;

上面结构体的实际使用：

static Ifx_P * const portLED = (Ifx_P *)&MODULE_P13;
......
#define LED_ON(x) (portLED->OMR.U = LED_PIN_RESET(x))

定义以上结构体时用到的各个子寄存器结构体的定义：

typedef union
{
    /** rief Unsigned access */
    unsigned int U;
    /** rief Signed access */
    signed int I;
    /** rief Bitfield access */
    Ifx_P_OUT_Bits B;
} Ifx_P_OUT;
......

typedef struct _Ifx_P_OUT_Bits
{
    unsigned int P0:1;                      /**< rief [0:0]  (rwh) */
    unsigned int P1:1;                      /**< rief [1:1]  (rwh) */
    unsigned int P2:1;                      /**< rief [2:2]  (rwh) */
    unsigned int P3:1;                      /**< rief [3:3]  (rwh) */
    unsigned int P4:1;                      /**< rief [4:4]  (rwh) */
    unsigned int P5:1;                      /**< rief [5:5]  (rwh) */
    unsigned int P6:1;                      /**< rief [6:6]  (rwh) */
    unsigned int P7:1;                      /**< rief [7:7]  (rwh) */
    unsigned int P8:1;                      /**< rief [8:8]  (rwh) */
    unsigned int P9:1;                      /**< rief [9:9]  (rwh) */
    unsigned int P10:1;                     /**< rief [10:10]  (rwh) */
    unsigned int P11:1;                     /**< rief [11:11]  (rwh) */
    unsigned int P12:1;                     /**< rief [12:12]  (rwh) */
    unsigned int P13:1;                     /**< rief [13:13]  (rwh) */
    unsigned int P14:1;                     /**< rief [14:14]  (rwh) */
    unsigned int P15:1;                     /**< rief [15:15]  (rwh) */
    unsigned int reserved_16:16;            /**< rief internal Reserved */
} Ifx_P_OUT_Bits;
......