FIFO

module syn_fifo        
(
    //input ports
    sys_clk               ,
    sys_rst_n             ,
 
    wr_en                 ,
    wr_data               ,
 
    rd_en                 ,
    //output ports 
    rd_data               ,
    rd_dv                 ,
 
    empty                 ,
    full  
);
 
// declare input ports
input                         sys_clk           ;  //system clock;
input                         sys_rst_n         ;  //system reset, low is active;
 
input                         wr_en             ;
input  [DWIDTH-1:0]           wr_data           ;
 
input                         rd_en             ;
 
 
// declare output ports
output [DWIDTH-1:0]           rd_data           ;
 
output                        rd_dv             ;
 
output                        empty             ;
 
output                        full              ;
 
//register define
reg    [DWIDTH-1:0]           rd_data           ;
reg                           rd_dv             ;
reg                           empty             ;
 
reg    [DWIDTH-1:0]           fifo_0            ;
reg    [DWIDTH-1:0]           fifo_1            ;
reg    [DWIDTH-1:0]           fifo_2            ;
reg    [DWIDTH-1:0]           fifo_3            ;
reg    [SIZE  -1:0]           current_fifo      ;
 
reg    [SIZE  -1:0]           wr_addr           ;
reg    [SIZE  -1:0]           rd_addr           ;
 
//wire define
wire   [SIZE  -1:0]           next_fifo         ;    
wire                          wr_fifo_0         ;
wire                          wr_fifo_1         ;
wire                          wr_fifo_2         ;
wire                          wr_fifo_3         ;
 
//parameter define 
parameter  DWIDTH    =    8                     ;
parameter  SIZE      =    3                     ;
 
/**********************************************************************************
**                              Main Program                                       
**                                                                                 
**********************************************************************************/
 
assign    wr_fifo_0 = wr_en && (wr_addr == 0)   ;
assign    wr_fifo_1 = wr_en && (wr_addr == 1)   ;
assign    wr_fifo_2 = wr_en && (wr_addr == 2)   ;
assign    wr_fifo_3 = wr_en && (wr_addr == 3)   ;
 
assign    next_fifo = current_fifo + 1'b1            ;   //the space is increased   
 
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        current_fifo <= 'b0;
    end
    else if (rd_en && wr_en) begin                         //read and write fifo the same time,the space of fifo is not change;
        current_fifo <= current_fifo;
    end
    else if (rd_en && (current_fifo != 'b0))               //read fifo ,the space of fifo is decrease;
        current_fifo <= current_fifo - 1'b1;
    else if (wr_en && (current_fifo[SIZE-1] != 1))begin    //wirte fifo ,the space of fifo is increase;
        current_fifo <= next_fifo;
    end
end
 
//generate the write address
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        wr_addr <= 'b0;
    end
   else if ((wr_en == 1'b1) && (full != 1'b1) ) begin
        wr_addr <= wr_addr + 1'b1;
    end
end
 
//wirte and read fifo
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        fifo_0 <= 'b0;
    end
    else if (wr_fifo_0) begin
        fifo_0 <= wr_data;
    end
end
 
//wirte and read fifo
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        fifo_1 <= 'b0;
    end
    else if (wr_fifo_1 ) begin
        fifo_1 <= wr_data;
    end
end
 
//wirte and read fifo
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        fifo_2 <= 'b0;
    end
    else if (wr_fifo_2) begin
        fifo_2 <= wr_data;
    end
end
 
//wirte and read fifo
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        fifo_3 <= 'b0;
    end
   else if (wr_fifo_3 ) begin
        fifo_3 <= wr_data;
    end
end
 
//generate the read address
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        rd_addr <= 'b0;
    end
   else if ((rd_en == 1'b1) && (empty != 1'b1) ) begin
        rd_addr <= rd_addr + 1'b1;
    end
end
 
//read fifo
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        rd_data <= 'b0;
    end
   else if (rd_en ==1'b1) begin
          case (rd_addr)
              0      :    rd_data <= fifo_0   ;
              1      :    rd_data <= fifo_1   ;
              2      :    rd_data <= fifo_2   ;
              3      :    rd_data <= fifo_3   ;
              default:    rd_data <= rd_data  ;    
          endcase  
    end
end
 
 
//generate read data and read valid signal
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        rd_dv   <= 'b0;
    end
    else if (rd_en && (current_fifo != 0))begin
        rd_dv    <= 'b1;
    end
    else begin
        rd_dv    <= 'b0;
    end
end
 
//generate fifo empty signal
always@(posedge sys_clk or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        empty <= 1'b0;
    end
    else if (rd_en && (current_fifo == 0)) begin           //when the space of the fifo is 0,and read the fifo is comning,then the fifo is empty;
        empty <= 1'b1;
    end
    else if (wr_en) begin
        empty <= 1'b0;
    end
end
 
assign    full      = current_fifo[SIZE-1]           ;    //when the space of the fifo is 4, then the fifo is full;
 
endmodule