转自：http://blog.sina.com.cn/s/blog_67be66e30100ra0u.html
用Xilinx ISE综合使用了IP核的设计，弹出警告错误
AR #29792 - XST - "WARNING:Xst:2211 - "file_name" line #: Instantiating black box module <module_name>"
该警告可无视，如想消除，见下
Description
Keywords: VHDL, EDIF, EDF, EDN, NGO, NGC
When a "black box" is instantiated, the following warning occurs:
"WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component <component_name>."
Solution
A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. Synthesis tools will generally report some kind of warning when a black box (an instantiated
component with no associated VHDL code) is detected.
Examples of black boxes include:
- CORE Generator modules
- Instantiated EDIF files
- Instantiated primitives
If you are instantiating a component that is represented by something other than HDL code, no response to the warning message is needed. If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure
that the component is properly represented by HDL code.
To avoid "black box" warning messages, add the following lines to your HDL code:
VHDL:
architecture <architecture_name>
:
attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";
:
begin
Verilog:
//synthesis attribute box_type <module_name> "black_box"
参考
http://www.xilinx.com/support/answers/29792.htm
http://www.xilinx.com/support/answers/9838.htm