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  • MT9v024总结

    S1:

    A typical READ or WRITE sequence begins by the master sending a start bit. After the
    start bit, the master sends the slave device’s 8-bit address. The last bit of the address
    determines if the request is a read or a write, where a “0” indicates a WRITE and a “1”
    indicates a READ. The slave device acknowledges its address by sending an acknowledge
    bit back to the master.
    If the request was a WRITE, the master then transfers the 8-bit register address to which
    a WRITE should take place. The slave sends an acknowledge bit to indicate that the
    register address has been received. The master then transfers the data 8 bits at a time,
    with the slave sending an acknowledge bit after each 8 bits. The MT9V024 uses 16-bit
    data for its internal registers, thus requiring two 8-bit transfers to write to one register.
    After 16 bits are transferred, the register address is automatically incremented, so that
    the next 16 bits are written to the next register address. The master stops writing by
    sending a start or stop bit.
    A typical READ sequence is executed as follows. First the master sends the write mode
    slave address and 8-bit register address, just as in the write request. The master then
    sends a start bit and the read mode slave address. The master then clocks out the register
    data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The
    register address is automatically incremented after every 16 bits is transferred. The data
    transfer is stopped when the master sends a no-acknowledge bit. The MT9V024 allows
    for 8-bit data transfers through the two-wire serial interface by writing (or reading) the
    most significant 8 bits to the register and then writing (or reading) the least significant 8
    bits to byte-wise address register (0x0F0).

    S2:

    16-Bit Write Sequence
    A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit
    given by the master, followed by the write address, starts the sequence. The image sensor
    then gives an acknowledge bit and expects the register address to come first, followed by
    the 16-bit data. After each 8-bit the image sensor gives an acknowledge bit. All 16 bits
    must be written before the register is updated. After 16 bits are transferred, the register
    address is automatically incremented, so that the next 16 bits are written to the next
    register. The master stops writing by sending a start or stop bit.

    16-Bit Read Sequence
    A typical read sequence is shown in Figure 10. First the master has to write the register
    address, as in a write sequence. Then a start bit and the read address specifies that a read
    is about to happen from the register. The master then clocks out the register data 8 bits
    at a time. The master sends an acknowledge bit after each 8-bit transfer. The register
    address is auto-incremented after every 16 bits is transferred. The data transfer is
    stopped when the master sends a no-acknowledge bit.

    8-Bit Write Sequence
    To be able to write 1 byte at a time to the register a special register address is added. The
    8-bit write is done by first writing the upper 8 bits to the desired register and then writing
    the lower 8 bits to the Bytewise Address register (R0xF0). The register is not updated until
    all 16 bits have been written. It is not possible to just update half of a register. In
    Figure 11, a typical sequence for 8-bit writing is shown. The second byte is written to the
    Bytewise register (R0xF0).

    8-Bit Read Sequence
    To read one byte at a time the same special register address is used for the lower byte.
    The upper 8 bits are read from the desired register. By following this with a read from the
    bytewise address register (R0xF0) the lower 8 bits are accessed (Figure 12). The master
    sets the no-acknowledge bits shown.

    S3:

    Sensor Operating Mode 当前使用的master mode,而且是simultaneous master (根据初始化代码,查询datasheet得出)

    S4:

    S5: slave address

    S6: LVDS 没有用到,从原理上可以看到,直接接地, 所以输出是 parallel output

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  • 原文地址:https://www.cnblogs.com/biglucky/p/4160230.html
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