用MedicalRadiate 3M主板上的FPGA产生500Hz可调PWM;3M板FPGA_CLK由STM32提供的72MHz frequence.
2.pwm.v
1 `timescale 1ns / 1ps 2 module pwm( 3 input clk_72m, 4 input rst_n, 5 output reg clk_50k, 6 output reg pwm_wave //generator 500Hz pwm 7 ); 8 reg rst_n1,rst_n2; 9 10 11 parameter PERIOD = 1440, 12 PULSEWIDTH = 720, 13 SIZE =11; //1440=10110100000,共11位 14 reg[SIZE-1:0] counter_div; 15 16 17 parameter DUTY = 40; //40% 18 19 reg [6:0] pwm_counter; 20 21 //reg X; 22 //reg duty; 23 ////////////////////////////////////////////////////////////////////////////////// 24 //异步复位，同步释放 25 always@(posedge clk_72m or negedge rst_n) 26 if(!rst_n) 27 rst_n1<=1'b0; 28 else 29 rst_n1<=1'b1; 30 31 always@(posedge clk_72m or negedge rst_n) 32 if(!rst_n) 33 rst_n2<=1'b0; 34 else 35 rst_n2<=rst_n1; 36 ////////////////////////////////////////////////////////////////////////////////// 37 //generator 50KHz clock; 38 always@(posedge clk_72m or negedge rst_n2) 39 if(!rst_n2) 40 counter_div<=0; 41 else if(counter_div<PERIOD-1) 42 counter_div<=counter_div+1'b1; 43 else 44 counter_div<=1'b0; 45 46 always@(posedge clk_72m or negedge rst_n2) 47 if(!rst_n2) 48 clk_50k<=1'b0; 49 else if(counter_div<PULSEWIDTH) 50 clk_50k<=1'b1; 51 else 52 clk_50k<=1'b0; 53 //Modelsim verify ok! 54 ////////////////////////////////////////////////////////////////////////////////// 55 56 always@(posedge clk_50k or negedge rst_n2) 57 begin 58 if(!rst_n2) 59 pwm_counter<=1'b0; 60 else if(pwm_counter==99) 61 pwm_counter<=1'b0; 62 else 63 pwm_counter<=pwm_counter+1'b1; 64 end 65 66 always@(posedge clk_50k or negedge rst_n2) 67 begin 68 if(!rst_n2) 69 pwm_wave <= 1'b0; 70 else if(pwm_counter==0) 71 pwm_wave <= 1'b1; 72 else if(pwm_counter<DUTY) 73 pwm_wave <= 1'b1; 74 else 75 pwm_wave <= 1'b0; 76 end 77 //Modelsim verify ok! 78 endmodule
2.pwm_tb.v
1 `timescale 1ns / 1ps 2 3 module pwm_tb; 4 5 // Inputs 6 reg clk_72m; 7 reg rst_n; 8 9 // Outputs 10 wire pwm_wave; 11 12 // Instantiate the Unit Under Test (UUT) 13 pwm pwm_tb ( 14 .clk_72m(clk_72m), 15 .rst_n(rst_n), 16 .clk_50k(clk_50k), 17 .pwm_wave(pwm_wave) 18 ); 19 20 parameter PERIOD = 14; 21 initial begin 22 // Initialize Inputs 23 clk_72m = 0; 24 forever 25 #(PERIOD/2) clk_72m=~clk_72m; 26 end 27 28 initial begin 29 rst_n = 0; 30 #100 rst_n=1; 31 end 32 33 34 endmodule
4.pwm_ucf.ucf
1 NET "clk_72m" LOC = "L22"; 2 NET "rst_n" LOC = "G21"; 3 NET "clk_50k" LOC = "C22"; 4 NET "pwm_wave" LOC = "C21"; 5 #Created by Constraints Editor (xc3s400-fg456-4) - 2013/05/16 6 NET "clk_72m" TNM_NET = clk_72m; 7 TIMESPEC TS_clk_72m = PERIOD "clk_72m" 14 ns HIGH 50%; 8 9 10 NET "clk_72m" CLOCK_DEDICATED_ROUTE = FALSE; 11 12 //由于FPGA_CLK没有接专用GCLK上面所以加上述说明语句