zoukankan      html  css  js  c++  java
  • [转]Example Design

    Description

    Attached to this Answer Record is an Example Design for using the AXI DMA in polled mode to transfer data to memory.

    Solution

    This design targets Zynq devices and uses a simple counter to drive the S2MM channel of the AXI DMA.

    Counter data is sent into and then read out of memory, and is finally sent out of the MM2S channel to an AXI Streaming FIFO. 

    The data received by the AXI Streaming FIFO is verified against the counter data. 

    The ARM controls DMA transfers via GP ports by accessing the AXI DMA core through its AXI Lite interface.

    It uses simple polling of the status register to manage DMA transfers.

    For more details about the design, refer to the dma_ex_polled/doc directory.





    The current version of this design was created in Vivado 2015.1.

    https://www.xilinx.com/support/answers/57561.html

  • 相关阅读:
    2
    作业5
    实验十
    作业 5 指针应用
    九九乘法表
    实验七(课堂练习)
    实验六 数组 (2)
    实验六 数组
    课堂实验5(求从m到n之间(包括m和n)所有素数的和)
    课堂实验5-2
  • 原文地址:https://www.cnblogs.com/ifpga/p/9027596.html
Copyright © 2011-2022 走看看