systemverilog

1.logic类型  

/*----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 2011/03/08 21:41:14
-- Design Name: 
-- Module Name:      
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies:  
--                                        
--                                                                                           
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--                                                  
----------------------------------------------------------------------------------*/

`timescale 1ns / 1ps

module hello_world();

import uvm_pkg::*;   

`include "uvm_macros.svh" 
 
localparam            CYCLE    =    5'd20    ;
 
logic        clock    ;
logic        reset    ;
 
initial begin   
    `uvm_info ("info1","Hello World!", UVM_LOW)   
    `uvm_info ("info2","Hello World!", UVM_LOW)  
    `uvm_info ("info3","Hello World!", UVM_LOW)  
    `uvm_info ("info4","Hello World!", UVM_LOW)  
end

initial begin
    clock = 0 ;
    forever # (CYCLE/2) clock = !clock ;
end 

initial begin
    reset = 1 ;
    #40
    reset = 0 ;
end 
 
 
//dut   u1
//(
///*input                     */.clk            (               ),
///*input                     */.rst_n        (               ),
///*input        [7:0]     */.rxd            (               ),
///*input                     */.rx_dv        (               ),
///*output     [7:0]     */.txd            (               ),
///*output                     */.tx_en        (               )
//);
  
 
endmodule

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