verilog 状态机键盘扫描

module key (clk,rst,key_up,led);
input clk,rst,key_up;
output reg [3:0] led;
parameter T10ms=31'd2_000_00;
reg clk_state;
reg [31:0] cnt;
parameter state_init=2'b00,state_click=2'b01,state_check=2'b10;
reg [1:0] current_state,next_state;
reg [3:0] num_click,num_check,led_on;
always @ (posedge clk or negedge rst)
if(!rst)
 begin
  cnt<=0;
  clk_state<=0;
 end
      else if(cnt==T10ms)
       begin
        cnt<=0;
        clk_state<=~clk_state;
       end
           else
            cnt<=cnt+1'b1;
always @ (posedge clk_state or negedge rst)
if(!rst)
 current_state<=state_init;
        else 
         current_state<=next_state;
always @ (posedge clk_state)
begin
 case(current_state)
 state_init: if(key_up) next_state<=state_init;
     else begin next_state<=state_click; num_click<=0;end
 state_click: if(key_up) begin next_state<=state_init;num_click<=0; end
     else begin num_click<=num_click+1;
       if(num_click==10)
         if(key_up)
           begin
           num_click<=0;
           next_state<=state_init;
           end
           else begin next_state<=state_check; num_check<=0;end
           end 
 state_check: if(key_up) begin next_state<=state_init; num_check<=0;led_on<=0;end
                         else begin num_check<=num_check+1;
         if(num_check==10)
         begin
         if(key_up)
          begin
           next_state<=state_init;
           num_check<=0;
          end
          else
          begin
          next_state<=state_check;
          num_check<=0;
          led_on<=led_on+1;
          end
         end end
endcase
end
always @ (current_state)
begin
led<=4'b1111;
case (current_state)
state_init: led<=4'b0101;
state_click: led<=4'b0111;
state_check: led<=led_on;
endcase
end
 
endmodule