error information
Illegal index into array of interfaces
the reason
link
The problem is that an array of instances (module, interface, or program), is not the same as an aggregate data type you know as an array variable. An array variable is a collection of identically typed elements.
With an array variable, you know what arrayvar[1].somthing refers to is identical in definition to arrayvar[2].something, except that is located somewhere else memory. You can simply multiply the variable index value by some constant value to find the offset in memory where it is located.
An array of instances is just a shortcut for declaring a set of numbered instances. Because of Verilog generate and parameter overrides statements, with an array of instances, you don't necessarily have a regular array. It's possible what arrayinst[1].something refers to something completely different than what arrayinst[2].something does. So the compiler requires a constant index value to know what that particular something is. You typically use a generate/for_loop to do this.
and please note
What you need to do is pull the loop outside the initial block