Timing requirements

Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
九神  10:39:18
criticalwarning
CrazyBingo  10:39:26
（1）全局clk输入
（2）转换成使能时钟
九神  10:39:52
实在是高
九神  10:40:12
把这个pixelclk当作enable用？
CrazyBingo  10:40:13
这两种我都干过
CrazyBingo  10:40:16
推荐（2）
CrazyBingo  10:40:28
边沿捕获一下 1个dff 其他数据全部1个dff同步

 

=========

/*
reg byte_cnt;
always@(posedge CMOS_PCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
CMOS_oDATA <= 16'b0;
CMOS_oCLK <= 1'b0;
byte_cnt <= 1'b0;
mrgb <= 16'b0;
end
else
begin
if((CMOS_VSYNC & CMOS_HREF)== 1'b1 && Frame_valid == 1'b1 )
begin
byte_cnt <= byte_cnt + 1'b1;
CMOS_oCLK <= 1'b1; //sys_we, clk??
case(byte_cnt)
1'b0 : begin CMOS_oDATA <= {8'b0,mrgb[7:0]}; end
1'b1 : begin mrgb <= {R[7:3],G[7:2],B[7:3]}; CMOS_oDATA <= {8'b0,mrgb[15:8]}; end //oddclk read mrgb
endcase
end
else
begin
CMOS_oDATA <= 16'b0;
CMOS_oCLK <= 1'b0;
byte_cnt <= 1'b0;
mrgb <= mrgb;
end
end
end
*/
//or 2
always@(posedge CMOS_PCLK or negedge iRST_N)
begin
if(!iRST_N)
CMOS_oCLK <= 0;
else if(Frame_valid == 1'b1)//(Frame_valid == 1'b1 && byte_state)
CMOS_oCLK <= CMOS_PCLK;
else
CMOS_oCLK <= 0;
end
//or 3
assign CMOS_oCLK = (Frame_valid == 1'b1) ? CMOS_PCLK : 1'b0;