状态机的写法

三段式状态机：

  用三个always语句块分别实现三个功能：同步状态转移、当前状态判断次态、输出

已10010串的检测为例 moore状态机

module fsmcheck (output z,
                           input   clk,
                           input   rst,
                           input   a
                          );
                 reg  [3:0]  nextstate, currentstate;
                 paramtet S0 = 4'b0000;
                 paramter S1 = 4'b0001;
                 paramter S2 = 4'b0010;
                 paramter S3 = 4'b0011;
                 paramter S4 = 4'b0100;
                 paramter S5 = 4'b0101;

                always @ (posedge clk or negedge rst）
                        begin
                           if(!rst)
                               currentstate <= S0;
                           else
                               currentstate <= nextstate;
                        end
                always @ (posedge clk or negedge rst)
                        begin
                           if(!rst)
                               currentstate <= S0;
                           else
                               begin
                                   case(currentstate)
                                       S0: if(a==1)
                                                nextstate <= S1;
                                             else
                                                nexrstate <= S0;
                                       S1: if (a==0)
                                                nextstate <= S2;
                                             else
                                                nextstate <= S1;
                                       S2: if(a==0)
                                                nextstate <= S3;
                                              else
                                                nextstate <= S1;

                                       S3: if(a==1)
                                                nextstate <= S4;
                                             else
                                                nextstate <= S0;
                                       S4: if(a==0)
                                                nextstate <= S5;
                                             else
                                                nextstate <= S1;
                                       S5: if(a==0)
                                                nextstate <= S3;
                                             else
                                                nextstate <= S1;
                                       default: nextstate <= S0;
                                   endcase
                              end
                  always @ (   rst or currentstate ）
                           begin
                             if(!rst)
                                z=0;
                             else
                                 case(currentstate)
                                      S0: z=0;
                                      S1: z=0;   
                                      S2: z=0;
                                      S3: z=0;
                                      S4: z=0;
                                      S5: z=1;
                                 endcase

                            end
endmodule